From patchwork Thu Nov 14 16:00:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 843137 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp359926wrc; Thu, 14 Nov 2024 08:03:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV5wGQ9X6N6KfSrDKE0N8F3h2lzZZlk8S4F5vxhckG3NB902WsJyceEd/BdStaOzD7ZEedL4Q==@linaro.org X-Google-Smtp-Source: AGHT+IFSIG65ZXjLTIGcSxT+5nKkYDgkSUf03+VJJ0wQ2gt0rVmJhi7ogq9qI2NEIMt+C2lfjHLd X-Received: by 2002:a67:e409:0:b0:4ad:4e61:596 with SMTP id ada2fe7eead31-4ad4e610866mr6091433137.0.1731600203824; Thu, 14 Nov 2024 08:03:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731600203; cv=none; d=google.com; s=arc-20240605; b=QEChnOfr9OJpWuyVnTKUnSkKxDOVsvbeBLILVRkvrkSuFxpSnCr24EV/EfLVN/Xj8m y9WhEhYCgn2rOFGCHn/OHCDmyo/BYM3nD3b/E4Gc+QN9rfG7WA6EgCHpkwiAem1Bl1do mdk/xJElWe9rG7xtfIQxexu1SBaiKgAvzd87GXXD4oFjQb0SSOMYLrqNbNNL38yNQAw8 BfiZjVBAWyuqUCge0pe4mJWpb1R9W4fw8jjqouaHNQ3iCQulUwFNWSkMWE+ps0GRr6Vn OODPBTps55WabqbV6MnKqfnBfylfPSlEvTQfLqrScN58MjVzrA8CroAWr8mIMKviXbNq oSFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=q3hq8/WORX9tjGeTrB15u911iYQPv1dQgSnGBISFTlA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=km9Fqk9irfeKlzuFvehotjpiRDB1ZV8igNV2KXyd3sfT/35+MjZIDdF8ZfZ7dFzt+/ 7mKi57onOb8r+t2+dC68eZdI0Rq4Z8FLK7jpa3TW8ML95+psIznFDTBKp1FIZoQMFRsH IGnaqhfoHSOQcz2XOMUfgtdRj62xHXEHg7/D7PxEiDl1J4XnRg7FodvpZZ9Kjcfjugt9 Ezq8x4zP5sfOzAb9Wy0PvduY/ONGEfugpI2IqBoKtjvgfWMEgWbTcOnKNFBHAeN9Fe31 GdCKDF5yV0F1Rve+ZOjkxJuRSlqNNn92Y05eJ6M7U5B4Au06sTFOOpHjIi+n7KMykORr RcOg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cmlz0NUQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4ad5987eae9si417540137.506.2024.11.14.08.03.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Nov 2024 08:03:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cmlz0NUQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBcJ8-0005m6-Uc; Thu, 14 Nov 2024 11:02:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBcI5-0004zy-IZ for qemu-devel@nongnu.org; Thu, 14 Nov 2024 11:01:56 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBcI3-0002F4-AO for qemu-devel@nongnu.org; Thu, 14 Nov 2024 11:01:52 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2e3d523a24dso687271a91.0 for ; Thu, 14 Nov 2024 08:01:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731600109; x=1732204909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=q3hq8/WORX9tjGeTrB15u911iYQPv1dQgSnGBISFTlA=; b=Cmlz0NUQdtgnoOegqJSXWKxJwjpM6H8bkqcetUsacOznDI5tYiS5QAMjHnjulV/Boo schnG8YS1m/QVMe6fAOQvjOXgo2PSvHVkSdhbcWJAXbVk0znJB9jjFi3TuLxiH0uXTUK ykPlO9Iz3XQpF/hoTvXREIgkZS5YS2XbCCKDAE84yWLcdHgEtV1JHIVzyyDNNuuQxJ41 zjMotGN6ytYBqCgU//uQwVJbF+/emmQaE99minwO+E7Lp1hgoJpxSkw9gAYNjsyVMwk7 qvLVKWmHbvvNOykIwLPZHqUAZIXy5wWmfkZwgx54BdE4egUoIIPq6ShthM3Yc5mf0dNR ttSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731600109; x=1732204909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q3hq8/WORX9tjGeTrB15u911iYQPv1dQgSnGBISFTlA=; b=e4/lOS30re3zBXimCJlJ6vy0xJhehssd6v/tEv3wTrLcUI3nEGRYhxqTDJG2RsVajz eR71vc9I3h57xwcOI+g0ui/ULwvd2ycJm+rtlbarwv2SXtposDsQ8Dk/f10Org2i0o1A 5X/6VTVBPP8UkOSZCjCo5OPxkSKjTlb52OES5RZM31WsApei9RNl0P+tiJ+h1HcgrUX6 nwCVZK52RTpFi9gBPJ6F4YAfgLoOvr93vD4NhRtKAmAJf26JVCxUKUU3lLrwV0aE2NmF fCd4X+0QP/ReW2hCHiq9jmiaEhnlTmltLZUaykpzNDZvYb824L0sFxYgTUNUZaVDbdr/ Mxdg== X-Gm-Message-State: AOJu0YxG/fKtYUz8sQqyD4xHtpyf7k3vIfsAl76ml0bxkUsCWltEABo1 O3FxmluBeJiSL1OgejTawo76+S7S9W/5PeGSNkEhTav7oyAsp41e90ZNYhLMnlE0tjSEdbpm22M + X-Received: by 2002:a17:90b:4acb:b0:2e2:d5fc:2847 with SMTP id 98e67ed59e1d1-2e9b177fe40mr32056117a91.30.1731600107271; Thu, 14 Nov 2024 08:01:47 -0800 (PST) Received: from stoup.. ([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.01.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:01:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 20/54] include/exec/tlb-common: Move CPUTLBEntryFull from hw/core/cpu.h Date: Thu, 14 Nov 2024 08:00:56 -0800 Message-ID: <20241114160131.48616-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUTLBEntryFull structures are no longer directly included within the CPUState structure. Move the structure definition out of cpu.h to reduce visibility. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/tlb-common.h | 63 +++++++++++++++++++++++++++++++++++++++ include/hw/core/cpu.h | 63 --------------------------------------- 2 files changed, 63 insertions(+), 63 deletions(-) diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h index dc5a5faa0b..300f9fae67 100644 --- a/include/exec/tlb-common.h +++ b/include/exec/tlb-common.h @@ -53,4 +53,67 @@ typedef struct CPUTLBDescFast { CPUTLBEntry *table; } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. + */ +struct CPUTLBEntryFull { + /* + * @xlat_section contains: + * - in the lower TARGET_PAGE_BITS, a physical section number + * - with the lower TARGET_PAGE_BITS masked off, an offset which + * must be added to the virtual address to obtain: + * + the ram_addr_t of the target RAM (if the physical section + * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) + * + the offset within the target MemoryRegion (otherwise) + */ + hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ + MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; + + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + + /* + * Additional tlb flags for use by the slow path. If non-zero, + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. + */ + uint8_t slow_flags[MMU_ACCESS_COUNT]; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ + union { + /* + * Cache the attrs and shareability fields from the page table entry. + * + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. + * For shareability and guarded, as in the SH and GP fields respectively + * of the VMSAv8-64 PTEs. + */ + struct { + uint8_t pte_attrs; + uint8_t shareability; + bool guarded; + } arm; + } extra; +}; + #endif /* EXEC_TLB_COMMON_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8eda0574b2..4364ddb1db 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -201,69 +201,6 @@ struct CPUClass { */ #define NB_MMU_MODES 16 -/* - * The full TLB entry, which is not accessed by generated TCG code, - * so the layout is not as critical as that of CPUTLBEntry. This is - * also why we don't want to combine the two structs. - */ -struct CPUTLBEntryFull { - /* - * @xlat_section contains: - * - in the lower TARGET_PAGE_BITS, a physical section number - * - with the lower TARGET_PAGE_BITS masked off, an offset which - * must be added to the virtual address to obtain: - * + the ram_addr_t of the target RAM (if the physical section - * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) - * + the offset within the target MemoryRegion (otherwise) - */ - hwaddr xlat_section; - - /* - * @phys_addr contains the physical address in the address space - * given by cpu_asidx_from_attrs(cpu, @attrs). - */ - hwaddr phys_addr; - - /* @attrs contains the memory transaction attributes for the page. */ - MemTxAttrs attrs; - - /* @prot contains the complete protections for the page. */ - uint8_t prot; - - /* @lg_page_size contains the log2 of the page size. */ - uint8_t lg_page_size; - - /* Additional tlb flags requested by tlb_fill. */ - uint8_t tlb_fill_flags; - - /* - * Additional tlb flags for use by the slow path. If non-zero, - * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. - */ - uint8_t slow_flags[MMU_ACCESS_COUNT]; - - /* - * Allow target-specific additions to this structure. - * This may be used to cache items from the guest cpu - * page tables for later use by the implementation. - */ - union { - /* - * Cache the attrs and shareability fields from the page table entry. - * - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability and guarded, as in the SH and GP fields respectively - * of the VMSAv8-64 PTEs. - */ - struct { - uint8_t pte_attrs; - uint8_t shareability; - bool guarded; - } arm; - } extra; -}; - /* * Data elements that are per MMU mode, minus the bits accessed by * the TCG fast path.