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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9bab70sm1417926b3a.152.2024.11.14.08.05.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:05:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 42/54] target/openrisc: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:18 -0800 Message-ID: <20241114160131.48616-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/openrisc/cpu.h | 8 +++++--- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 39 +++++++++++++++++++++------------------ 3 files changed, 27 insertions(+), 22 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c9fe9ae12d..e177ad8b84 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -22,6 +22,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "fpu/softfloat-types.h" /** @@ -306,9 +307,10 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info); #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool openrisc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t ra); extern const VMStateDescription vmstate_openrisc_cpu; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f2..6aa04ff7d3 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -237,7 +237,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .restore_state_to_opc = openrisc_restore_state_to_opc, #ifndef CONFIG_USER_ONLY - .tlb_fill = openrisc_cpu_tlb_fill, + .tlb_fill_align = openrisc_cpu_tlb_fill_align, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .cpu_exec_halt = openrisc_cpu_has_work, .do_interrupt = openrisc_cpu_do_interrupt, diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..eafab356a6 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -104,39 +104,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, cpu->env.lock_addr = -1; } -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool openrisc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int excp = EXCP_DPF; int prot; hwaddr phys_addr; + /* TODO: alignment faults not currently handled. */ + if (mmu_idx == MMU_NOMMU_IDX) { /* The mmu is disabled; lookups never fail. */ get_phys_nommu(&phys_addr, &prot, addr); - excp = 0; } else { bool super = mmu_idx == MMU_SUPERVISOR_IDX; int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC : access_type == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ); - excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + int excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + + if (unlikely(excp)) { + if (probe) { + return false; + } + raise_mmu_exception(cpu, addr, excp); + cpu_loop_exit_restore(cs, retaddr); + } } - if (likely(excp == 0)) { - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - return true; - } - if (probe) { - return false; - } - - raise_mmu_exception(cpu, addr, excp); - cpu_loop_exit_restore(cs, retaddr); + memset(out, 0, sizeof(*out)); + out->phys_addr = phys_addr; + out->prot = prot; + out->lg_page_size = TARGET_PAGE_BITS; + out->attrs = MEMTXATTRS_UNSPECIFIED; + return true; } hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)