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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id m69si2128677qgm.21.2014.12.09.10.44.33 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 09 Dec 2014 10:44:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:41940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XyPlx-0000k3-JH for patch@linaro.org; Tue, 09 Dec 2014 13:44:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XyPl9-0008PK-SD for qemu-devel@nongnu.org; Tue, 09 Dec 2014 13:43:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XyPl5-0008EC-1k for qemu-devel@nongnu.org; Tue, 09 Dec 2014 13:43:43 -0500 Received: from mail-lb0-f182.google.com ([209.85.217.182]:51743) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XyPl4-0008E6-Rg for qemu-devel@nongnu.org; Tue, 09 Dec 2014 13:43:39 -0500 Received: by mail-lb0-f182.google.com with SMTP id f15so1105829lbj.27 for ; Tue, 09 Dec 2014 10:43:38 -0800 (PST) X-Received: by 10.152.37.38 with SMTP id v6mr23747431laj.10.1418150617982; Tue, 09 Dec 2014 10:43:37 -0800 (PST) MIME-Version: 1.0 Received: by 10.112.150.135 with HTTP; Tue, 9 Dec 2014 10:43:16 -0800 (PST) In-Reply-To: <1416242878-876-7-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> <1416242878-876-7-git-send-email-greg.bellows@linaro.org> From: Peter Maydell Date: Tue, 9 Dec 2014 18:43:16 +0000 Message-ID: To: Greg Bellows X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.217.182 Cc: Sergey Fedorov , QEMU Developers , Fabian Aggeler , "Edgar E. Iglesias" Subject: Re: [Qemu-devel] [PATCH v11 06/26] target-arm: add secure state bit to CPREG hash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 17 November 2014 at 16:47, Greg Bellows wrote: > Added additional NS-bit to CPREG hash encoding. Updated hash lookup > locations to specify hash bit currently set to non-secure. > > Signed-off-by: Greg Bellows > Reviewed-by: Peter Maydell > > --- > > v8 -> v9 > - Fixed CP_REG_NS_MASK > - Changed ENCODE_CP_REG argument order so ns follows is64 > - Replaced use of CP_REG_NS_MASK with CP_REG_NS_SHIFT > - Changed add_cpreg_to_hashtable argument order so ns follows is64 > - Replaced use of SCR_NS with ARM_CP_SECSTATE_NS on registration > - Undid global replace of Aarch# with AArch# in translate.c > > v5 -> v6 > - Globally replace Aarch# with AArch# > --- > target-arm/cpu.h | 25 ++++++++++++++++++++----- > target-arm/helper.c | 7 ++++--- > target-arm/translate.c | 14 +++++++++----- > 3 files changed, 33 insertions(+), 13 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index dd7d229..532f698 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -879,6 +879,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq); > * Crn, Crm, opc1, opc2 fields > * 32 or 64 bit register (ie is it accessed via MRC/MCR > * or via MRRC/MCRR?) > + * non-secure/secure bank (AArch32 only) > * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. > * (In this case crn and opc2 should be zero.) > * For AArch64, there is no 32/64 bit size distinction; > @@ -896,9 +897,16 @@ void armv7m_nvic_complete_irq(void *opaque, int irq); > #define CP_REG_AA64_SHIFT 28 > #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) > > -#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ > - (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ > - ((crm) << 7) | ((opc1) << 3) | (opc2)) > +/* To enable banking of coprocessor registers depending on ns-bit we > + * add a bit to distinguish between secure and non-secure cpregs in the > + * hashtable. > + */ > +#define CP_REG_NS_SHIFT 29 > +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) > + > +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ > + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ > + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) We forgot about the uses of ENCODE_CP_REG in kvm32.c, so this breaks compile on ARM. Since I've already put these patches into target-arm.next, I'm going to just squash in the fix: thanks -- PMM --- a/target-arm/kvm32.c +++ b/target-arm/kvm32.c @@ -51,17 +51,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) struct kvm_one_reg idregs[] = { { .id = KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0), + | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), .addr = (uintptr_t)&midr, }, { .id = KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 1, 0, 0), + | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), .addr = (uintptr_t)&id_pfr0, }, { .id = KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 2, 0, 0), + | ENCODE_CP_REG(15, 0, 0, 0, 2, 0, 0), .addr = (uintptr_t)&id_isar0, }, {