From patchwork Mon Feb 26 08:20:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129598 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3359669lja; Mon, 26 Feb 2018 00:27:39 -0800 (PST) X-Google-Smtp-Source: AG47ELuhYDD3NzytRi7hzK6t0ov/MHR1OtX+GxJeIRh4jzpy8HYU/u+9PIxgHvqqW92IbzZMUk8Z X-Received: by 2002:a17:902:14b:: with SMTP id 69-v6mr4526441plb.209.1519633659507; Mon, 26 Feb 2018 00:27:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519633659; cv=none; d=google.com; s=arc-20160816; b=insN+c/ysRrguTQqXSNpaETCGOIEexWrEGCof7v7WYuO8esRQm5OtdoufH4OGd7Gg4 DR4m2nYTLLR57Bq70Lr0WeXJIe2Vo1bxLFO9RD/t7hAmNhJLsUmDql2gBmYY6/NS7Or9 h+59/40ghnNeO+Cwk9775cxcZBubpuTqoYYx8GSO0iwOpesgd/vHAr5BYjsRMHDf56vF jmlUaAFW2JOljI5v8of+a2B5mlSTWi4w23t6a5LCflPv/xzP/qvER+8r8R1UezoTlFit jLroRTnSc+CILNUV2kf8nJ/tHg7V560pR9CRtat0OTEEPYrJ8qMb+kbWGyb79wat0jKq O85g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=EGJE0Nu47ttv68Cv7IDoZdvRv6F03kpbdP4X9eVpyD0=; b=lwc1//tCXfu/lHDGONmMg37Mm0Ji2Sb9i2iG30DbazJ9xi5Xp/E5Z8NzQ4XEwD16A6 bpzQ+6GIDzRn8RV39ifrYaaEvsHrUZ0nLWP8z6bmLVN7RPRYiMxL45Tq8U9iTss67S7r 0HgdVFVtBxJpoEiJ5g0gH7puQpDD9QfMewGweI+bIE2msrJLJlLhx9gCbGaTkjChA7Hi DqAvZ3SOXkqWp2vR+92FwrexVYhvo4P2d/mHHHyXeLhueqNEzvOuPY14KgTx8Fe64T4n PjEzblL/jY8xhC186ErzuM2HFJxtpdbBVaYi3lU8zWcibiR6cRT2beyObB+e4yuORoSu e/mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=db7VIA95; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f23-v6si6600728plk.810.2018.02.26.00.27.39; Mon, 26 Feb 2018 00:27:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=db7VIA95; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752855AbeBZI1h (ORCPT + 10 others); Mon, 26 Feb 2018 03:27:37 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:46002 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752865AbeBZI1e (ORCPT ); Mon, 26 Feb 2018 03:27:34 -0500 Received: by mail-pl0-f67.google.com with SMTP id v9-v6so6862904plp.12 for ; Mon, 26 Feb 2018 00:27:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=EGJE0Nu47ttv68Cv7IDoZdvRv6F03kpbdP4X9eVpyD0=; b=db7VIA95FUrzght6E19A2huPjfrsEijQBVn16eA8R5RQGOomHH9u+0qfmdUWnDa2N8 /sUlzXqzBC2XiVRukO7Bwe7eVTO9u/2MNNrH6Cqneypvkno4XYFjNQ7y43dqGwFnkvQm umTbWy8t92pJCQWT0LTFIfpr7zSHX8n6LuKDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=EGJE0Nu47ttv68Cv7IDoZdvRv6F03kpbdP4X9eVpyD0=; b=Zu2T9Ebh01zG/nXzyHIX7pncIqeglYInJAjrGYDy/NKu5ZwXDCEMLPZ4BersxOffkO IeJPKH7WhwYoEfMKX0X2sVS28gn1oL+HBdHMmfeOtiWWvtaYyuRG3EByLQCc+NHhSHBi 0Q3wE5PpMh4A3Q/E1qNOgkVOAu45fNM76Etonbs4VdXQX204/o0nsrNFjbxWVSl7XeLX JCzJMtVTG143j7t5wlIImjsV3eqHjxS3T/dc+KpwCMwRv5n65+FdeArtfB1QTwQVKXd0 7IR5shs3d/gvw/263/S6DPRmDdSa9quP3BFFM0/RJ4bGkj4Peo7bosNRKxri0IiwcDCf i/fQ== X-Gm-Message-State: APf1xPB1eQjs5Pmum261YCe1lKdQNXOmaCKG9pqavx3VFdfE4KSHK88d fMaJfcgRyMJ/qAFBhifjiFQ7PQ== X-Received: by 2002:a17:902:a70f:: with SMTP id w15-v6mr9595442plq.79.1519633652951; Mon, 26 Feb 2018 00:27:32 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id o86sm1422706pfi.87.2018.02.26.00.27.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 00:27:32 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, Russell King , linux-arm-kernel@lists.infradead.org (moderated list:ARM PORT), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 49/52] arm: Add icache invalidation on switch_mm for Cortex-A15 Date: Mon, 26 Feb 2018 16:20:23 +0800 Message-Id: <1519633227-29832-50-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> References: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier ** Not yet queued for inclusion in mainline ** In order to avoid aliasing attacks against the branch predictor, Cortex-A15 require to invalidate the BTB when switching from one user context to another. The only way to do so on this CPU is to perform an ICIALLU, having set ACTLR[0] to 1 from secure mode. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Alex Shi --- arch/arm/mm/proc-v7-2level.S | 10 ++++++++++ arch/arm/mm/proc-v7-3level.S | 10 ++++++++++ arch/arm/mm/proc-v7.S | 23 ++++++++++++++++++++++- 3 files changed, 42 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 0422e58b..6d81ed7 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -40,7 +40,16 @@ * Note that we always need to flush BTAC/BTB if IBE is set * even on Cortex-A8 revisions not affected by 430973. * If IBE is not set, the flush BTAC/BTB won't do anything. + * + * Cortex-A15 requires ACTLR[0] to be set from secure in order + * for the icache invalidation to also invalidate the BTB. */ +ENTRY(cpu_v7_icinv_switch_mm) +#ifdef CONFIG_MMU + mcr p15, 0, r0, c7, c5, 0 @ ICIALLU + /* Fall through to switch_mm... */ +#endif + ENTRY(cpu_v7_btbinv_switch_mm) #ifdef CONFIG_MMU mov r2, #0 @@ -67,6 +76,7 @@ ENTRY(cpu_v7_switch_mm) bx lr ENDPROC(cpu_v7_switch_mm) ENDPROC(cpu_v7_btbinv_switch_mm) +ENDPROC(cpu_v7_icinv_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index a25450b..af6d7b1 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -54,6 +54,15 @@ * Set the translation table base pointer to be pgd_phys (physical address of * the new TTB). */ +ENTRY(cpu_v7_icinv_switch_mm) +#ifdef CONFIG_MMU + /* + * Cortex-A15 requires ACTLR[0] to be set from secure in order + * for the icache invalidation to also invalidate the BTB. + */ + mcr p15, 0, r0, c7, c5, 0 @ ICIALLU + /* Fall through to switch_mm... */ +#endif ENTRY(cpu_v7_btbinv_switch_mm) #ifdef CONFIG_MMU mcr p15, 0, r0, c7, c5, 6 @ flush BTAC/BTB @@ -69,6 +78,7 @@ ENTRY(cpu_v7_switch_mm) ret lr ENDPROC(cpu_v7_switch_mm) ENDPROC(cpu_v7_btbinv_switch_mm) +ENDPROC(cpu_v7_icinv_switch_mm) #ifdef __ARMEB__ #define rl r3 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index ff7018a..f385933 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -227,6 +227,26 @@ ENDPROC(cpu_ca9mp_do_resume) globl_equ cpu_ca17_do_resume, cpu_v7_do_resume #endif +/* + * Cortex-A15 + */ + globl_equ cpu_ca15_proc_init, cpu_v7_proc_init + globl_equ cpu_ca15_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca15_reset, cpu_v7_reset + globl_equ cpu_ca15_do_idle, cpu_v7_do_idle + globl_equ cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_ca15_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + globl_equ cpu_ca15_switch_mm, cpu_v7_icinv_switch_mm +#else + globl_equ cpu_ca15_switch_mm, cpu_v7_switch_mm +#endif +#ifdef CONFIG_ARM_CPU_SUSPEND + globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend + globl_equ cpu_ca15_do_resume, cpu_v7_do_resume +#endif + #ifdef CONFIG_CPU_PJ4B globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext @@ -568,6 +588,7 @@ __v7_setup_stack: @ define struct processor (see and proc-macros.S) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 define_processor_functions ca17, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #ifndef CONFIG_ARM_LPAE define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 @@ -689,7 +710,7 @@ __v7_ca12mp_proc_info: __v7_ca15mp_proc_info: .long 0x410fc0f0 .long 0xff0ffff0 - __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup + __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info /*