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[209.85.220.65]) by mx.google.com with SMTPS id p35-v6sor12066792qve.50.2018.10.15.08.32.34 for (Google Transport Security); Mon, 15 Oct 2018 08:32:34 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UHAS4B48; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lOxhVwiZMGTDMExac/LzweOoDpoIyRiEe92zktpSuQs=; b=UHAS4B48IwK2TiceCVi8EA8lJkIcZ77RoitAnjTkU+88dtZtAa5ylg3il/QWHDPFiX GXLLpbB2wsMnGTYrtIndUetmA6DN5bWTytpFdtH2plZA3jJ2GgqQWgFF7taJqM7xl8SI R37e8FeozuGhkqdyk760ZO26OsHIxKbc0NlPk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lOxhVwiZMGTDMExac/LzweOoDpoIyRiEe92zktpSuQs=; b=eSh1wfHNx9rALKjyGItSAZoy/lj34Y7f4HQRpXOu8G0fssU2hkfPQlrDCKnErsQo4x Gj0sMS8GGzb3vHWE8+65DXk1bUXv+eUh/fAg/zSNPgsHqwcdkYZIcW468KRzpcRQd+U7 EnOP2ypuhv4izE8YIHYxYNXw8ZGuer2DC5akK09faAfyk8DcrAXQKqa9uP2FqdNTANM+ 9USZzqompVedHMq78ABJ/RmsgN7vzr3UhP5T9Z6S03F2qYQ7kNjiwHib5I9f/RG3LDvn 5dChRI2VwCr9/3OKQLHp5YQMM+BC6E2STIA8mnCJmYTS+5DVJmvhhFgPXLNoAJjkZAHT 9r0A== X-Gm-Message-State: ABuFfojFWM7FCP1ESMwcK3Tx90fCTOHY09q2JF0gii5ZjMHVYkcqif83 94wBP6mg+fZ5K76xulC3mlVhgmf9 X-Google-Smtp-Source: ACcGV63FxdvcEgaaPkYhYZhUgd7LA6pZgGkJib/YG/lFvg6cXt5HjpQOSUKTxpeJhDvWeTH138nLdA== X-Received: by 2002:a0c:d78e:: with SMTP id z14-v6mr17067564qvi.92.1539617554004; Mon, 15 Oct 2018 08:32:34 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([72.71.243.63]) by smtp.googlemail.com with ESMTPSA id g82-v6sm10087768qkh.24.2018.10.15.08.32.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Oct 2018 08:32:33 -0700 (PDT) From: David Long To: , Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.14 12/24] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Date: Mon, 15 Oct 2018 11:32:06 -0400 Message-Id: <1539617538-22328-13-git-send-email-dave.long@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1539617538-22328-1-git-send-email-dave.long@linaro.org> References: <1539617538-22328-1-git-send-email-dave.long@linaro.org> From: Marc Zyngier Commit 0c47ac8cd157727e7a532d665d6fb1b5fd333977 upstream. In order to avoid aliasing attacks against the branch predictor on Cortex-A15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. Signed-off-by: Marc Zyngier Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/kvm_mmu.h | 5 +++++ arch/arm/kvm/hyp/hyp-entry.S | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) -- 2.5.0 diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 85d48c9..082b286 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -255,6 +255,11 @@ static inline void *kvm_get_hyp_vector(void) return kvm_ksym_ref(__kvm_hyp_vector_bp_inv); } + case ARM_CPU_PART_CORTEX_A15: + { + extern char __kvm_hyp_vector_ic_inv[]; + return kvm_ksym_ref(__kvm_hyp_vector_ic_inv); + } #endif default: { diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S index e789f52..918a05d 100644 --- a/arch/arm/kvm/hyp/hyp-entry.S +++ b/arch/arm/kvm/hyp/hyp-entry.S @@ -73,6 +73,28 @@ __kvm_hyp_vector: #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR .align 5 +__kvm_hyp_vector_ic_inv: + .global __kvm_hyp_vector_ic_inv + + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + W(add) sp, sp, #1 /* Reset 7 */ + W(add) sp, sp, #1 /* Undef 6 */ + W(add) sp, sp, #1 /* Syscall 5 */ + W(add) sp, sp, #1 /* Prefetch abort 4 */ + W(add) sp, sp, #1 /* Data abort 3 */ + W(add) sp, sp, #1 /* HVC 2 */ + W(add) sp, sp, #1 /* IRQ 1 */ + W(nop) /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + + b decode_vectors + + .align 5 __kvm_hyp_vector_bp_inv: .global __kvm_hyp_vector_bp_inv @@ -92,6 +114,8 @@ __kvm_hyp_vector_bp_inv: mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ isb +decode_vectors: + #ifdef CONFIG_THUMB2_KERNEL /* * Yet another silly hack: Use VPIDR as a temp register.