From patchwork Fri Jun 19 14:32:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 223719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42EF8C433E1 for ; Fri, 19 Jun 2020 16:37:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1786121924 for ; Fri, 19 Jun 2020 16:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592584666; bh=xCvhklzmLu/JLE8mtxHrM3M2TUrYdKLNq2hDaxul1rw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=aQYJzAwIRgxsN2jedZQ4v+6q5vNysgdvJopNqH2Wj3RSQUN7pUy06fnnfaLxrcy87 FW4rIoevai3pSUC4Hi55bavZcu+uNzU5loUKbswXHZQlf33QVnLdDZmADwq66fSKCs CAJVbogCq4/WcfDKqfSmT0T98uOHrOntK1PxUeqg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389071AbgFSOsS (ORCPT ); Fri, 19 Jun 2020 10:48:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:40506 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389067AbgFSOsP (ORCPT ); Fri, 19 Jun 2020 10:48:15 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2C0BA20DD4; Fri, 19 Jun 2020 14:48:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592578095; bh=xCvhklzmLu/JLE8mtxHrM3M2TUrYdKLNq2hDaxul1rw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p3OYh2OLILiZ3XJurpcCMn2FCkMVVczWypFcrngSwkVUA+lcvTlsqsMREZPn94avb /0wpONJ4Hq7wxF+15jOpTLJ09rxOJcFfPBQWSw/fjSbzf5C9imlchqmiYO36TUdGDW CjUbMjDXSIF9KuJdIcSHQZCKU51EzuzQZVoxcX7w= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Evan Green , Shobhit Srivastava , Andy Shevchenko , Mark Brown , Sasha Levin Subject: [PATCH 4.14 080/190] spi: pxa2xx: Apply CS clk quirk to BXT Date: Fri, 19 Jun 2020 16:32:05 +0200 Message-Id: <20200619141637.586222192@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619141633.446429600@linuxfoundation.org> References: <20200619141633.446429600@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Evan Green [ Upstream commit 6eefaee4f2d366a389da0eb95e524ba82bf358c4 ] With a couple allies at Intel, and much badgering, I got confirmation from Intel that at least BXT suffers from the same SPI chip-select issue as Cannonlake (and beyond). The issue being that after going through runtime suspend/resume, toggling the chip-select line without also sending data does nothing. Add the quirk to BXT to briefly toggle dynamic clock gating off and on, forcing the fabric to wake up enough to notice the CS register change. Signed-off-by: Evan Green Cc: Shobhit Srivastava Cc: Andy Shevchenko Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-pxa2xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index b73fde1de463..1579eb2bc29f 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -156,6 +156,7 @@ static const struct lpss_config lpss_platforms[] = { .tx_threshold_hi = 48, .cs_sel_shift = 8, .cs_sel_mask = 3 << 8, + .cs_clk_stays_gated = true, }, { /* LPSS_CNL_SSP */ .offset = 0x200,