From patchwork Tue Oct 27 13:52:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 307229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B34AC388F9 for ; Tue, 27 Oct 2020 17:02:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BBE2207C3 for ; Tue, 27 Oct 2020 17:02:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603818144; bh=xPTYDqcKFPNokPQ4YG2zVjKrCaVG4vsCuNK5PQRUCM4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=o30JuV3p7/ZFI1q26jMkggDVZH6LMvfUuO83VrIfACwGY1K6TfU0ocMvT/+O1kqrB YDVs2gbS5CIU5KPMb3kEknvD9GzKMBAWiqpbjD/7asnzqdV2+y3KMP++sERZjNfzB9 hIrGXdfEJrUmm3rJRDsLj50DxseGevtCyTcJvApA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1793747AbgJ0PIG (ORCPT ); Tue, 27 Oct 2020 11:08:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:40384 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1793164AbgJ0PGP (ORCPT ); Tue, 27 Oct 2020 11:06:15 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1B81B206E5; Tue, 27 Oct 2020 15:06:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603811174; bh=xPTYDqcKFPNokPQ4YG2zVjKrCaVG4vsCuNK5PQRUCM4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Onofla2ZqIN/N1RFMhKjOA+bnP1ozV3eTuey7PFQPgzOlutB8PsZNHuNgv+mBc0uU lnKoS/EZrLAkPF3kCzi55kkB2v7EAI/nxLfXYnSXt8jHwpVLFU/lPSkW6yzq2lWBpy YHq+VV0oyWibZydmhsh/Clsx38sLI22JSSDbAENU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Athira Rajeev , Madhavan Srinivasan , Michael Ellerman , Sasha Levin Subject: [PATCH 5.8 399/633] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints Date: Tue, 27 Oct 2020 14:52:22 +0100 Message-Id: <20201027135541.429691096@linuxfoundation.org> X-Mailer: git-send-email 2.29.1 In-Reply-To: <20201027135522.655719020@linuxfoundation.org> References: <20201027135522.655719020@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Athira Rajeev [ Upstream commit 3b6c3adbb2fa42749c3d38cfc4d4d0b7e096bb7b ] PMU counter support functions enforces event constraints for group of events to check if all events in a group can be monitored. Incase of event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ), not all constraints are applicable, say the threshold or sample bits. But current code includes pmc5 and pmc6 in some group constraints (like IC_DC Qualifier bits) which is actually not applicable and hence results in those events not getting counted when scheduled along with group of other events. Patch fixes this by excluding PMC5/6 from constraints which are not relevant for it. Fixes: 7ffd948 ("powerpc/perf: factor out power8 pmu functions") Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/1600672204-1610-1-git-send-email-atrajeev@linux.vnet.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/perf/isa207-common.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 4c86da5eb28ab..0b5c8f4fbdbfd 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -269,6 +269,15 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) mask |= CNST_PMC_MASK(pmc); value |= CNST_PMC_VAL(pmc); + + /* + * PMC5 and PMC6 are used to count cycles and instructions and + * they do not support most of the constraint bits. Add a check + * to exclude PMC5/6 from most of the constraints except for + * EBB/BHRB. + */ + if (pmc >= 5) + goto ebb_bhrb; } if (pmc <= 4) { @@ -335,6 +344,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) } } +ebb_bhrb: if (!pmc && ebb) /* EBB events must specify the PMC */ return -1;