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[v2,0/3] qcom: serial_msm: calculate UARTDM_CSR automatically

Message ID 20240415-b4-msm-serial-bitrate-v2-0-b7a048adc6a3@linaro.org
Headers show
Series qcom: serial_msm: calculate UARTDM_CSR automatically | expand

Message

Caleb Connolly April 15, 2024, 3:03 p.m. UTC 
The msm serial UART controller has a bit clock divider register which
much be programmed based on the UART clock. This changes per soc and
currently is expected to be specified in DT or otherwise selected per
board.

This series fixes the apq8016 and ipq4019 clock drivers to return the
programmed UART clock rate in clk_set_rate(), it then uses this clock
rate and the hardcoded baud rate supported by this driver to calculate
the correct value for the UARTDM_CSR register.

---
Changes in v2:
- use CONFIG_VAL(DEBUG_UART_CLOCK) for debug uart clk_rate.
- Link to v1: https://lore.kernel.org/r/20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org

---
Caleb Connolly (3):
      clk/qcom: apq8016: return valid rate when setting UART clock
      clk/qcom: ipq4019: return valid rate when setting UART clock
      serial: msm: calculate bit clock divider

 doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
 drivers/clk/qcom/clock-apq8016.c               |  4 +-
 drivers/clk/qcom/clock-ipq4019.c               |  2 +-
 drivers/serial/serial_msm.c                    | 87 +++++++++++++++++++++-----
 4 files changed, 73 insertions(+), 30 deletions(-)
---
base-commit: 42f6978987336cff3d98d9cc4643c54a1eb0f36d

// Caleb (they/them)

Comments

Caleb Connolly April 15, 2024, 6:45 p.m. UTC | #1 
On Mon, 15 Apr 2024 16:03:37 +0100, Caleb Connolly wrote:
> The msm serial UART controller has a bit clock divider register which
> much be programmed based on the UART clock. This changes per soc and
> currently is expected to be specified in DT or otherwise selected per
> board.
> 
> This series fixes the apq8016 and ipq4019 clock drivers to return the
> programmed UART clock rate in clk_set_rate(), it then uses this clock
> rate and the hardcoded baud rate supported by this driver to calculate
> the correct value for the UARTDM_CSR register.
> 
> [...]

Applied, thanks!

[1/3] clk/qcom: apq8016: return valid rate when setting UART clock
      commit: f191853d77899c8a845f20f62068c4ee68d2a020
[2/3] clk/qcom: ipq4019: return valid rate when setting UART clock
      commit: b49b68909b5f4030869051073857d086c5292461
[3/3] serial: msm: calculate bit clock divider
      commit: 1aadf1ebc32c8bf7f4eae9ab2abaf63c1fea7d4f

Best regards,