From patchwork Thu Jun 7 06:09:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9154 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id F03B023F0A for ; Thu, 7 Jun 2012 06:05:56 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id A9A9CA18AA3 for ; Thu, 7 Jun 2012 06:05:56 +0000 (UTC) Received: by ggnf1 with SMTP id f1so167317ggn.11 for ; Wed, 06 Jun 2012 23:05:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=g4ChqtXGzmDYZpDN+NODYmbI79XBbjaT8AMrcaW7WpI=; b=FzPFsMvTLjrVykBlfy/dch3WYyTlcuJzkCyr+Z+35l8amU9Na5g85/f/31+zHekk0L bdJHNhuicIwwizHO4JDhYTihQEXQ6ZANNU3C4QIlCGW3KBqtGdgUfJBcdwWG+pXlVj74 DvpGS9mGl3X8T+ytKhaspxv2PO6/d9rn/uVlQ0+z00H3ORbdLAbOAd5oVJesQ10yr/fV keqLH9yZvbiYnrCxKnJ9syLhzNMtAcYOeQVkIHRlf72ulbUQH9pxHIHQS+wg9xhF8yFo OIK/1Y6o27X9x/bjBNFAWiSlqI7r/iC+8mLPNu4J9wn2l09bzMigIdQR8+Nn4wGvBhVL 5XJA== Received: by 10.50.87.227 with SMTP id bb3mr460997igb.57.1339049156028; Wed, 06 Jun 2012 23:05:56 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp124526ibb; Wed, 6 Jun 2012 23:05:55 -0700 (PDT) Received: by 10.68.131.10 with SMTP id oi10mr4696115pbb.122.1339049155263; Wed, 06 Jun 2012 23:05:55 -0700 (PDT) Received: from mailout4.samsung.com (mailout4.samsung.com. [203.254.224.34]) by mx.google.com with ESMTP id pk6si4144441pbc.60.2012.06.06.23.05.54; Wed, 06 Jun 2012 23:05:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M58004P6GX9EXM0@mailout4.samsung.com>; Thu, 07 Jun 2012 15:05:54 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-78-4fd044c244e7 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 6C.06.05800.2C440DF4; Thu, 07 Jun 2012 15:05:54 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5800J8XGX3ZV30@mmp1.samsung.com>; Thu, 07 Jun 2012 15:05:53 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 3/8 V2] EXYNOS: PINMUX: Add pinmux support for I2C Date: Thu, 07 Jun 2012 11:39:49 +0530 Message-id: <1339049394-4816-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1339049394-4816-1-git-send-email-rajeshwari.s@samsung.com> References: <1339049394-4816-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jAd1DLhf8DZY2clg8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK2L/zCUvBKsmKx/cdGxg3iXYxcnJICJhI3GrazARh i0lcuLeerYuRi0NIYBGjxJpLbewQzkQmiaePlrOAVLEJGElsPTmNEcQWEZCQ+NV/FcxmFmhk lNix2hXEFhZwkpiy7ig7iM0ioCoxcdMksBpeAXeJ1ZNOQm1TkDg29SsriM0p4CGx5dtJsBoh oJqP7zazTmDkXcDIsIpRNLUguaA4KT3XUK84Mbe4NC9dLzk/dxMj2PvPpHYwrmywOMQowMGo xMPL4XjBX4g1say4MvcQowQHs5IIr0DZeX8h3pTEyqrUovz4otKc1OJDjNIcLErivE3WQNUC 6YklqdmpqQWpRTBZJg5OqQbGzBiDl6bPT4Zt/bn9zdXXx5tYPJZmcas8yJLf8zUqxC4m/77u wkNN39q2Fzkb39lz5tietvBv+suZpP81ePfP/qixf4Kodau36Z3wluPLogzVT7ttcjSRLFu9 rvW2w6wAJm1mm4CrcgvurRVJ+vc7bGr2R+2rj7WWvj/k8EVmp6lUeiHL/jpmJZbijERDLeai 4kQABqa0OfoBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQk9Votit+twUC0Pi1WRaPUeTXcwNKgAzidW5Mn3HrsZdh2RBPMq4XdpgTdCAiGY0doL5aS+ This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass Acked-by: Simon Glass --- Changes in V2: - Aligned the pinmux functionality as per the latest comments. This patch depends on the following patch: "[U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 8 ++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 597e487..d3314a1 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -182,6 +182,48 @@ static void exynos5_sromc_config(int flags) } } +static void exynos5_i2c_config(int peripheral, int flags) +{ + + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -200,6 +242,16 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SROMC: exynos5_sromc_config(flags); break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos5_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..b861d7d 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,