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[203.254.224.33]) by mx.google.com with ESMTP id st8si29419541pbc.295.2012.06.20.03.35.56; Wed, 20 Jun 2012 03:35:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00C6VW3UEW50@mailout3.samsung.com>; Wed, 20 Jun 2012 19:35:55 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-73-4fe1a78b0b5e Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 33.C7.05800.B87A1EF4; Wed, 20 Jun 2012 19:35:55 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00HP6W2XTK70@mmp1.samsung.com>; Wed, 20 Jun 2012 19:35:55 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com, banajit.g@samsung.com Subject: [PATCH 1/9] ARCH: SPL: Add parametric board initializer Date: Wed, 20 Jun 2012 16:10:02 +0530 Message-id: <1340188810-18871-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> References: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKJMWRmVeSWpSXmKPExsVy+t9jAd3u5Q/9DT7uUrZ4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CV8eb3ZuaCyUoVXR8tGxjnSHcxcnJICJhIbL3byQxh i0lcuLeerYuRi0NIYBGjxOwdr9lAEkICE5kk1l9WArHZBIwktp6cxghiiwhISPzqv8oI0sAs sJBRYsLMm2CThAUcJL7t3craxcjBwSKgKtE53QTE5BXwkLhy0Ahil4LEsalfWUFsTgFPiWln drFArPKQeH7+EvsERt4FjAyrGEVTC5ILipPScw31ihNzi0vz0vWS83M3MYI9/0xqB+PKBotD jAIcjEo8vDyzH/oLsSaWFVfmHmKU4GBWEuEt7wAK8aYkVlalFuXHF5XmpBYfYpTmYFES522y vuAvJJCeWJKanZpakFoEk2Xi4JRqYEzep3znXEp/9165ivufOH0bbm/J3LtOMbioa65/wRwP M7XZXnpXlwi9dUqTq619nGKkN9t3i0yY9vbjn7Z29LzeNa9UYhdbV7HsBrd//xVFZ797y9Sg VOUXM0tziu2kSdF7Hx83V86uYfO5c27hRxeGiyqiPOf0rNb75USZP8itW3RVwEu+RomlOCPR UIu5qDgRAH+zPpr4AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmJBRlsRKLCnyhULAkHgAQWQdT6omX89SUe57Rt9Y+dqfW7UXJWQmc/G5DFV5dQ8Pq76xBu Add a structure for table-driven configuration mechanism such that no recompilation is needed to update the configuration parameters, rather than hard-coding board initialization parameters. Signed-off-by: Che-Liang Chiou Signed-off-by: Abhilash Kesavan Signed-off-by: Tom Wai-Hong Tam Signed-off-by: Simon Glass Signed-off-by: Rajeshwari Shinde --- arch/arm/include/asm/arch-exynos/spl.h | 95 ++++++++++++++++++++++++++++++++ 1 files changed, 95 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/spl.h diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h new file mode 100644 index 0000000..1d79239 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/spl.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_EXYNOS_SPL_H__ +#define __ASM_ARCH_EXYNOS_SPL_H__ + +#include + +enum boot_mode { + /* + * Assign the OM pin values for respective boot modes. + * Exynos4 does not support spi boot and the mmc boot OM + * pin values are the same across Exynos4 and Exynos5. + */ + BOOT_MODE_MMC = 4, + BOOT_MODE_SERIAL = 20, + /* Boot based on Operating Mode pin settings */ + BOOT_MODE_OM = 32, + BOOT_MODE_USB, /* Boot using USB download */ +}; + +/* Parameters of early board initialization in SPL */ +struct spl_machine_param { + /* Add fields as and when required */ + u32 signature; + u32 version; /* Version number */ + u32 size; /* Size of block */ + /** + * Parameters we expect, in order, terminated with \0. Each parameter + * is a single character representing one 32-bit word in this + * structure. + * + * Valid characters in this string are: + * + * Code Name + * v mem_iv_size + * m mem_type + * u uboot_size + * b boot_source + * f frequency_mhz (memory frequency in MHz) + * a ARM clock frequency in MHz + * s serial base address + * i i2c base address for early access (meant for PMIC) + * r board rev GPIO numbers used to read board revision + * (lower halfword=bit 0, upper=bit 1) + * M Memory Manufacturer name + * \0 termination + */ + char params[12]; /* Length must be word-aligned */ + u32 mem_iv_size; /* Memory channel interleaving size */ + enum ddr_mode mem_type; /* Type of on-board memory */ + /* + * U-boot size - The iROM mmc copy function used by the SPL takes a + * block count paramter to describe the u-boot size unlike the spi + * boot copy function which just uses the u-boot size directly. Align + * the u-boot size to block size (512 bytes) when populating the SPL + * table only for mmc boot. + */ + u32 uboot_size; + enum boot_mode boot_source; /* Boot device */ + enum mem_manuf mem_manuf; /* Memory Manufacturer */ + unsigned frequency_mhz; /* Frequency of memory in MHz */ + unsigned arm_freq_mhz; /* ARM Frequency in MHz */ + u32 serial_base; /* Serial base address */ + u32 i2c_base; /* i2c base address */ +} __attribute__((__packed__)); + +/** + * Validate signature and return a pointer to the parameter table. If the + * signature is invalid, call panic() and never return. + * + * @return pointer to the parameter table if signature matched or never return. + */ +struct spl_machine_param *spl_get_machine_params(void); + +#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */