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Date: Thu, 27 Dec 2012 11:33:23 +0530 Message-id: <1356588203-24838-17-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1356588203-24838-1-git-send-email-rajeshwari.s@samsung.com> References: <1356588203-24838-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWyRsSkSlfv8e0Ag0XzBCwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlzJp1lLXgsHLFvHmtbA2MX6W7GDk5JARMJC6cPssO YYtJXLi3nq2LkYtDSGApo0TD2cnsMEVL5vSwQiQWMUrsWnQVypnIJPGpcSILSBWbgJHE1pPT GEFsEQEJiV/9V8FsZoEYidf7f7CB2MICjhK3L/wCi7MIqEpcObGRCcTmFfCU2NFzkAVim4LE salfWUFsTqD4hCvLwOqFBDwkvuw5zwbRKyDxbfIhoHoOoHpZiU0HmEHukRC4zSax8UM7K8Qc SYmDK26wTGAUXsDIsIpRNLUguaA4KT3XSK84Mbe4NC9dLzk/dxMjMCBP/3smvYNxVYPFIUYB DkYlHl5F69sBQqyJZcWVuYcYJTiYlUR4p28GCvGmJFZWpRblxxeV5qQWH2L0AbpkIrOUaHI+ MFrySuINjU3MTY1NLY2MzExNcQgrifM2e6QECAmkJ5akZqemFqQWwYxj4uCUamAs9KuR/+Xy IvHTQv3Guxuk5b5f+CLXvOxcYKJ1/vnqH5tTdh1vW6s945tqxgsV1+ps17O+HGzaYcrf6rSW n1q76Xx6bvm6kzs8Ju1QnrvhefbbZfOf+na3OJ0JeRkcJXbxHMeL7qxfM+VL+d9MSr5V2LKx 5S/7th8cS2RFQh7JbjZ5cm7/Qb3bSizFGYmGWsxFxYkAaosoZHUCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsVy+t9jAV29x7cDDPqesls8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzJg16yhrwWHl innzWtkaGL9KdzFyckgImEgsmdPDCmGLSVy4t56ti5GLQ0hgEaPErkVXWSGciUwSnxonsoBU sQkYSWw9OY0RxBYRkJD41X8VzGYWiJF4vf8HG4gtLOAocfvCL7A4i4CqxJUTG5lAbF4BT4kd PQdZILYpSByb+hVsMydQfMKVZWD1QgIeEl/2nGebwMi7gJFhFaNoakFyQXFSeq6RXnFibnFp Xrpecn7uJkZwuD+T3sG4qsHiEKMAB6MSD6+i9e0AIdbEsuLK3EOMEhzMSiK80zcDhXhTEiur Uovy44tKc1KLDzH6AF01kVlKNDkfGIt5JfGGxibmpsamliYWJmaWOISVxHmbPVIChATSE0tS s1NTC1KLYMYxcXBKNTAqPbrevTkvsWjyqv/bSsodFrdPmMcya895PkmO2etPzP5+Y2/E4i5P qz0PS2/v+O0snJ8weXN/gOu+azNYMpzbdYoM1Pd+fPU6Srv3TdACtosn/iUeE1iZJ8R4eGvS wwdp1aWz1z/K7TzZLry146yO+bvAA+uWf3we4uMfubd5/7v6NUdt2pZLKrEUZyQaajEXFScC ANfQQb+kAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQm3Jl2mIT7DrHqKtmQ5qK3gR3uqMsiBfMrnRc2t7+Cct62Ul9Cg7D9gsQXGdK8JJ2GbLSIX This patch adds FDT support to the SPI driver. Signed-off-by: Simon Glass Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes since V1: - Corrected compilation error for non DT and removed extra blank line. drivers/spi/exynos_spi.c | 96 +++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 3e6c18f..be60ada 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -28,16 +29,20 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* Information about each SPI controller */ struct spi_bus { enum periph_id periph_id; s32 frequency; /* Default clock frequency, -1 for none */ struct exynos_spi *regs; int inited; /* 1 if this bus is ready for use */ + int node; }; /* A list of spi buses that we know about */ static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS]; +static unsigned int bus_count; struct exynos_spi_slave { struct spi_slave slave; @@ -50,7 +55,7 @@ struct exynos_spi_slave { static struct spi_bus *spi_get_bus(unsigned dev_index) { - if (dev_index < EXYNOS5_SPI_NUM_CONTROLLERS) + if (dev_index < bus_count) return &spi_bus[dev_index]; debug("%s: invalid bus %d", __func__, dev_index); @@ -347,21 +352,100 @@ static inline struct exynos_spi *get_spi_base(int dev_index) (dev_index - 3); } +/* + * Read the SPI config from the device tree node. + * + * @param blob FDT blob to read from + * @param node Node offset to read from + * @param bus SPI bus structure to fill with information + * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing + */ +static int spi_get_config(const void *blob, int node, struct spi_bus *bus) +{ + bus->node = node; + bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg"); + bus->periph_id = pinmux_decode_periph_id(blob, node); + + if (bus->periph_id == PERIPH_ID_NONE) { + debug("%s: Invalid peripheral ID %d\n", __func__, + bus->periph_id); + return -FDT_ERR_NOTFOUND; + } + + /* Use 500KHz as a suitable default */ + bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + + return 0; +} + +/* + * Process a list of nodes, adding them to our list of SPI ports. + * + * @param blob fdt blob + * @param node_list list of nodes to process (any <=0 are ignored) + * @param count number of nodes to process + * @param is_dvc 1 if these are DVC ports, 0 if standard I2C + * @return 0 if ok, -1 on error + */ +static int process_nodes(const void *blob, int node_list[], int count) +{ + int i; + + /* build the i2c_controllers[] for each controller */ + for (i = 0; i < count; i++) { + int node = node_list[i]; + struct spi_bus *bus; + + if (node <= 0) + continue; + + bus = &spi_bus[i]; + if (spi_get_config(blob, node, bus)) { + printf("exynos spi_init: failed to decode bus %d\n", + i); + return -1; + } + + debug("spi: controller bus %d at %p, periph_id %d\n", + i, bus->regs, bus->periph_id); + bus->inited = 1; + bus_count++; + } + + return 0; +} + /* Sadly there is no error return from this function */ void spi_init(void) { - int i; + int count; + +#ifdef CONFIG_OF_CONTROL + int node_list[EXYNOS5_SPI_NUM_CONTROLLERS]; + const void *blob = gd->fdt_blob; + + count = fdtdec_find_aliases_for_id(blob, "spi", + COMPAT_SAMSUNG_EXYNOS_SPI, node_list, + EXYNOS5_SPI_NUM_CONTROLLERS); + if (process_nodes(blob, node_list, count)) + return; + +#else struct spi_bus *bus; - for (i = 0; i < EXYNOS5_SPI_NUM_CONTROLLERS; i++) { - bus = &spi_bus[i]; - bus->regs = get_spi_base(i); - bus->periph_id = PERIPH_ID_SPI0 + i; + for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) { + bus = &spi_bus[count]; + bus->regs = get_spi_base(count); + bus->periph_id = PERIPH_ID_SPI0 + count; /* Although Exynos5 supports upto 50Mhz speed, * we are setting it to 10Mhz for safe side */ bus->frequency = 10000000; bus->inited = 1; + bus->node = 0; + bus_count = EXYNOS5_SPI_NUM_CONTROLLERS; } +#endif }