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[203.254.224.34]) by mx.google.com with ESMTP id fd8si3157620pad.220.2013.03.22.07.03.41; Fri, 22 Mar 2013 07:03:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MK2000YWF1VDUN0@mailout4.samsung.com>; Fri, 22 Mar 2013 23:03:40 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 9A.71.20872.CB46C415; Fri, 22 Mar 2013 23:03:40 +0900 (KST) X-AuditID: cbfee68d-b7f786d000005188-47-514c64bc8739 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 84.62.13494.BB46C415; Fri, 22 Mar 2013 23:03:40 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MK200DNCF1X6M80@mmp1.samsung.com>; Fri, 22 Mar 2013 23:03:39 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH] EXYNOS: SPI: Minimise access to SPI FIFO level Date: Fri, 22 Mar 2013 19:39:37 +0530 Message-id: <1363961377-18835-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPLMWRmVeSWpSXmKPExsWyRsSkRndPik+gwbRGHouH62+yWHQcaWG0 mHL4C4vFty3bGC3e7u1kd2D1mN1wkcXjzrU9bB5n7+xg9OjbsooxgCWKyyYlNSezLLVI3y6B K+P+6XesBT2iFa9efmFuYGwV6GLk5JAQMJHoW7qEBcIWk7hwbz1bFyMXh5DAUkaJ82cvs8AU 7TqznxnEFhJYxCix9T4nRNFEJokVZ++BJdgEjCS2npzGCGKLCEhI/Oq/CmYzC8RIvN7/gw3E FhawlziycArYUBYBVYkttw+B1fAKeEh07H/ODLFMQeLY1K+sEPZrNoklS90h6gUkvk0+BNTL ARSXldh0AKpcUuLgihssExgFFzAyrGIUTS1ILihOSi8y1CtOzC0uzUvXS87P3cQIDMzT/571 7mC8fcD6EGMy0LiJzFKiyfnAwM4riTc0NjOyMDUxNTYytzQjTVhJnFetxTpQSCA9sSQ1OzW1 ILUovqg0J7X4ECMTB6dUA2N0zpK8/ykGH7tzGGwz90ifDZtxLcpp/5+93dKVlsyWDS/0a/e+ FA1WWpfwbOa5mdz757k9v/7g4VvGjR/sNjVv2LNoGlecCtOi7xFsaZbrvjNWd33dbvXAJcOc k29Z30mnhXtXmtS/fJW1f32ZRuwum135cr7f1GNVlSSm/f3j9DrphGpD6hwlluKMREMt5qLi RABtGC4nYgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLIsWRmVeSWpSXmKPExsVy+t9jAd09KT6BBo92MVs8XH+TxaLjSAuj xZTDX1gsvm3Zxmjxdm8nuwOrx+yGiywed67tYfM4e2cHo0ffllWMASxRDYw2GamJKalFCql5 yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUCblRTKEnNKgUIBicXFSvp2 mCaEhrjpWsA0Ruj6hgTB9RgZoIGENYwZ90+/Yy3oEa149fILcwNjq0AXIyeHhICJxK4z+5kh bDGJC/fWs4HYQgKLGCW23ufsYuQCsicySaw4ew+siE3ASGLryWmMILaIgITEr/6rYDazQIzE 6/0/wJqFBewljiycwgJiswioSmy5fQishlfAQ6Jj/3OoZQoSx6Z+ZZ3AyL2AkWEVo2hqQXJB cVJ6rpFecWJucWleul5yfu4mRnDgP5PewbiqweIQowAHoxIPr4aOd6AQa2JZcWXuIUYJDmYl Ed5t/j6BQrwpiZVVqUX58UWlOanFhxiTgbZPZJYSTc4HRmVeSbyhsYm5qbGppYmFiZklacJK 4rwHW60DhQTSE0tSs1NTC1KLYLYwcXBKNTA6pTU8SXF8fXTZZKd68529R/yzLr+2eqDOtl1x V5lN87mJmutFFFZFHF30M94g9vGE3z93cyam9xf8ZFpjNKFm8xeh5yvCbzuH6XgJLHF9/vT8 hGuFcZsMMhjD9UVnpf9MuOhtL36S5azyQr3ju1//rbrv3qzx/M8Hx8NXl9d6rF3SflJwUbWw EktxRqKhFnNRcSIATaaS/MACAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQm8kDQ/vxpgDM33spTV/hSM8ngYnOS1JJ7xP6JsjjN08gR/I3U4WRjXOR+T/ZhsoYjv2q0q Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output logic which might run at 1/8th of the 40MHz SPI speed (just a guess). Reduce access to this register by filling up and emptying FIFOs more completely, rather than just one word each time around the inner loop. Since the rxfifo value will now likely be much greater that what we read before we fill the txfifo, we only fill the txfifo halfway. This is because if the txfifo is empty, but the rxfifo has data in it, then writing too much data to the txfifo may overflow the rxfifo as data arrives. This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow. Signed-off-by: Simon Glass Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- drivers/spi/exynos_spi.c | 31 +++++++++++++++++-------------- 1 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index c19e227..7bbf9ce 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -260,33 +260,36 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, /* Keep the fifos full/empty. */ spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); - if (tx_lvl < spi_slave->fifo_size && out_bytes) { + while (tx_lvl < spi_slave->fifo_size / 2 && out_bytes) { temp = txp ? *txp++ : 0xff; writel(temp, ®s->tx_data); out_bytes--; + tx_lvl++; } if (rx_lvl > 0 && in_bytes) { - temp = readl(®s->rx_data); - if (!rxp && !stopping) { - in_bytes--; - } else if (spi_slave->skip_preamble) { - if (temp == SPI_PREAMBLE_END_BYTE) { - spi_slave->skip_preamble = 0; - stopping = 0; + while (rx_lvl > 0 && in_bytes) { + temp = readl(®s->rx_data); + if (!rxp && !stopping) { + in_bytes--; + } else if (spi_slave->skip_preamble) { + if (temp == SPI_PREAMBLE_END_BYTE) { + spi_slave->skip_preamble = 0; + stopping = 0; + } + } else { + *rxp++ = temp; + in_bytes--; } - } else { - *rxp++ = temp; - in_bytes--; + toread--; + rx_lvl--; } - toread--; - } /* * We have run out of input data, but haven't read enough * bytes after the preamble yet. Read some more, and make * sure that we transmit dummy bytes too, to keep things * going. */ - else if (in_bytes && !toread) { + } else if (in_bytes && !toread) { assert(!out_bytes); toread = out_bytes = in_bytes; txp = NULL;