From patchwork Tue May 17 07:38:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 67925 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp1929447qge; Tue, 17 May 2016 00:37:42 -0700 (PDT) X-Received: by 10.28.86.10 with SMTP id k10mr21246488wmb.96.1463470662908; Tue, 17 May 2016 00:37:42 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id dm2si1885435wjb.137.2016.05.17.00.37.42; Tue, 17 May 2016 00:37:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EF6E7A76BA; Tue, 17 May 2016 09:37:37 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Yas0nJkm5DbW; Tue, 17 May 2016 09:37:37 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C87FFA76CC; Tue, 17 May 2016 09:37:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21D1FA7550 for ; Tue, 17 May 2016 09:37:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I96Tl3LH3ugq for ; Tue, 17 May 2016 09:37:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by theia.denx.de (Postfix) with ESMTPS id 4B6C7A7532 for ; Tue, 17 May 2016 09:37:13 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u4H7b1fp006885; Tue, 17 May 2016 16:37:05 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u4H7b1fp006885 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1463470625; bh=oOUUzKplFYNo8Ac9vj9NgqTTjaiX61fLj3266eCGFqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rOg33LLkvXJirdZORvZxohMnz8jwCC0aUSSzLXEUuETJaVKcJvUHuR9DNh7WdJ53U 0ahItMOIZOnZj280Dnr65nbUv8H4Vlr5MSqYhlXdYqxjb2O+v3aJrOMlc8bd0ei+qh eXRMHGEVOdRQ8PWXXPOj569u6LXPsChNyhfvEyztoe0TqmDsIEtJ3IFQcWHqS+KlZN RlccJA2bYxu81UVA4l/76XHKLiAGmg/KnUOvqe7rJKUEMP7SzNMYbmFc40Oj2x2YoP PYd+XT552L5D7marSUBB9sZ9ve2amsfvJ3HAE8yr9TsbFmr5ro9hPGGYhvMCPWjwhK isDfSYOS19RXA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 17 May 2016 16:38:08 +0900 Message-Id: <1463470688-13772-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463470688-13772-1-git-send-email-yamada.masahiro@socionext.com> References: <1463470688-13772-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 3/3] arm64: rename __asm_flush_dcache_level to __asm_dcache_level X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada --- arch/arm/cpu/armv8/cache.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 6aaecf3..46f25e6 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -14,15 +14,15 @@ #include /* - * void __asm_flush_dcache_level(level) + * void __asm_dcache_level(level) * - * clean and invalidate one level cache. + * flush or invalidate one level cache. * * x0: cache level * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ -ENTRY(__asm_flush_dcache_level) +ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ @@ -57,14 +57,14 @@ loop_way: b.ge loop_set ret -ENDPROC(__asm_flush_dcache_level) +ENDPROC(__asm_dcache_level) /* * void __asm_flush_dcache_all(int invalidate_only) * * x0: 0 clean & invalidate, 1 invalidate only * - * clean and invalidate all data cache by SET/WAY. + * flush or invalidate all data cache by SET/WAY. */ ENTRY(__asm_dcache_all) mov x1, x0 @@ -87,7 +87,7 @@ loop_level: and x12, x12, #7 /* x12 <- cache type */ cmp x12, #2 b.lt skip /* skip if no cache or icache */ - bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ skip: add x0, x0, #1 /* increment cache level */ cmp x11, x0