From patchwork Tue Jun 7 12:03:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 69498 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp1939014qgf; Tue, 7 Jun 2016 05:03:23 -0700 (PDT) X-Received: by 10.28.7.208 with SMTP id 199mr2360281wmh.74.1465301003070; Tue, 07 Jun 2016 05:03:23 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id 4si23343857wml.43.2016.06.07.05.03.22; Tue, 07 Jun 2016 05:03:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A6E3E4B91E; Tue, 7 Jun 2016 14:03:12 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jdwZcyt_fcWC; Tue, 7 Jun 2016 14:03:12 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 54067A7516; Tue, 7 Jun 2016 14:03:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4F3DD4B94B for ; Tue, 7 Jun 2016 14:02:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jcisZKjftAjW for ; Tue, 7 Jun 2016 14:02:55 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by theia.denx.de (Postfix) with ESMTPS id 477E84B91E for ; Tue, 7 Jun 2016 14:02:50 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id u57C2bdP019177; Tue, 7 Jun 2016 21:02:42 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u57C2bdP019177 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1465300962; bh=GHoiSIL72e7lUiw0Lj1qylk/mBRXVDi1Sf9EUrMSlzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rK0UXFozXwxAjTNwIo0Pqp08tVYDLtMjJDMHXCuKwKr7zB87uVbZJYgyn6o/cu+Q+ DjG89/LNl+ww806MY62AMwHILSIv7DMsm/mRG8As9SOJwfr1/fDX9j3qM8wOC7E1AQ 5NPP3tbg5rh0VSSZzxIjjMTqm6TamkD54Pm22AL4CiC3OtFRJPkTwhINElLHf4OuFN 4X1OmN2DMj2uaoJx0hW1NBO2Ek+iU9qfFQyq5gG5nBVrZZpX1eg9P+EXj93An/uIu4 e8kipjAi/PhMF/s3KknqpJuGDwznOcHQdjnbm6mdrB3C7S5AGuKuaLGx3Ee8ZKsU1t 6uZ7CtHR1Hkyg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 7 Jun 2016 21:03:47 +0900 Message-Id: <1465301027-1650-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465301027-1650-1-git-send-email-yamada.masahiro@socionext.com> References: <1465301027-1650-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 5/5] ARM: uniphier: insert dsb barrier to ensure the visibility X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" I noticed secondary CPUs sometimes fail to wake up, and the root cause seems that the "sev" instruction is sent before the preceding register write access is observed by the secondary CPUs. The read-back of the accessed register cannot guarantee the order. This commit uses "dsb sy" barrier to ensure the order between the write access to UNIPHIER_SMPCTRL_ROM_RSV0 and the "sev" instruction. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c index 64412e0..3b75eaa 100644 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void) rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); - readq(rom_boot_rsv0); /* relax */ unmap_sysmem(rom_boot_rsv0); uniphier_smp_setup(); - asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ + asm("dsb sy\n" /* Ensure the visibility of ROM_RSV0 write */ + "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ }