From patchwork Thu Jun 16 05:46:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 70140 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp91556qgy; Wed, 15 Jun 2016 22:45:04 -0700 (PDT) X-Received: by 10.28.207.136 with SMTP id f130mr2599876wmg.29.1466055904289; Wed, 15 Jun 2016 22:45:04 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id uv1si3354144wjc.96.2016.06.15.22.45.04; Wed, 15 Jun 2016 22:45:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 24F75A753B; Thu, 16 Jun 2016 07:45:03 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tNrbr17pGmsV; Thu, 16 Jun 2016 07:45:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A111A751E; Thu, 16 Jun 2016 07:45:02 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DD699A751E for ; Thu, 16 Jun 2016 07:44:58 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bE5RZMFoUAwY for ; Thu, 16 Jun 2016 07:44:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-08.nifty.com (conuserg-08.nifty.com [210.131.2.75]) by theia.denx.de (Postfix) with ESMTPS id 2BA48A74DB for ; Thu, 16 Jun 2016 07:44:53 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-08.nifty.com with ESMTP id u5G5ifFR028932; Thu, 16 Jun 2016 14:44:42 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com u5G5ifFR028932 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1466055882; bh=NHVpML/lUGl4BJZjxn0yMUOEAanGJdCaU4VSPIRHs3c=; h=From:To:Cc:Subject:Date:From; b=1IiTTC5O6aaGNmpzqWq9gFYeVr+Fl7rPlh43Jj3UrWaYJ7fbp/cniDswF+D+zO4Zv uFBpg099ndkomfVkH5ecJod328HDmNnCyKoBO/wv4vL48aycMGNkBO0bidm035neLn U6M8VaUEBKZoHh9IeiK7+xwqE5gjbkVZxHnT895Nq85Eamyok7BLax93uZqYcJAAZ3 sE4suWoJCTgPj/Qh4b6oBHX3CfF8jEKfHffA8RY1U2VURg7A4blYjqEqEIyWsQGei9 TUFLsMFbAcVcjiBo9j188KnHstKF1iuH2URE1tmDHMzLcasSsn9fS22HWkfUdQo9Fy InYPTTce+Ulqg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 16 Jun 2016 14:46:01 +0900 Message-Id: <1466055961-975-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH] ARM: uniphier: reserve memory for DRAM PHY training on PH1-LD20 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The DRAM PHY on PH1-LD20 is able to calibrate PHY parameters periodically. This improves PHY adjustment against the voltage and temperature deviation. Instead, it requires 64 byte scratch memory in each DRAM channel for the dynamic training. The memory regions must be reserved in DT before jumping to the kernel. The scratch area can be anywhere in each DRAM channel, but the DRAM init code in SPL currently assigns it at the end of each channel. So, it makes sense to reserve the regions dynamically by U-Boot instead of statically embedding it in the DT in Linux. Anyway, a boot-loader should know much more about memory initialization than the kernel. Signed-off-by: Masahiro Yamada --- arch/arm/Kconfig | 1 + arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/dram_init.c | 40 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e75c4c0..5aaae96 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -801,6 +801,7 @@ config ARCH_UNIPHIER select SPL select OF_CONTROL select SPL_OF_CONTROL + select OF_LIBFDT select DM select SPL_DM select DM_GPIO diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index ae763ad..b2374db 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -32,6 +32,7 @@ config ARCH_UNIPHIER_LD20 bool "UniPhier PH1-LD20 SoC" select ARM64 select SPL_SEPARATE_BSS + select OF_BOARD_SETUP endchoice diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index ef0e2e8..06300de 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -9,6 +9,9 @@ #include #include +#include "init.h" +#include "soc-info.h" + DECLARE_GLOBAL_DATA_PTR; static const void *get_memory_reg_prop(const void *fdt, int *lenp) @@ -81,3 +84,40 @@ void dram_init_banksize(void) (unsigned long)gd->bd->bi_dram[i].size); } } + +#ifdef CONFIG_OF_BOARD_SETUP +/* + * The DRAM PHY requires 64 byte scratch area in each DRAM channel + * for its dynamic PHY training feature. + */ +int ft_board_setup(void *fdt, bd_t *bd) +{ + const struct uniphier_board_data *param; + unsigned long rsv_addr; + const unsigned long rsv_size = 64; + int ch, ret; + + if (uniphier_get_soc_type() != SOC_UNIPHIER_LD20) + return 0; + + param = uniphier_get_board_param(); + if (!param) { + printf("failed to get board parameter\n"); + return -ENOENT; + } + + for (ch = 0; ch < param->dram_nr_ch; ch++) { + rsv_addr = param->dram_ch[ch].base + param->dram_ch[ch].size; + rsv_addr -= rsv_size; + + ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); + if (ret) + return ret; + + printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", + rsv_addr, rsv_size); + } + + return 0; +} +#endif