From patchwork Thu Aug 25 12:03:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 74682 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp800300qga; Thu, 25 Aug 2016 05:02:02 -0700 (PDT) X-Received: by 10.195.13.18 with SMTP id eu18mr7169920wjd.121.1472126522849; Thu, 25 Aug 2016 05:02:02 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id s21si13886714wmd.21.2016.08.25.05.02.02; Thu, 25 Aug 2016 05:02:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 839F74B811; Thu, 25 Aug 2016 14:02:01 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AqIekJmwjL3Q; Thu, 25 Aug 2016 14:02:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D4924B624; Thu, 25 Aug 2016 14:02:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4673B4B624 for ; Thu, 25 Aug 2016 14:01:52 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 388i97u3EsVt for ; Thu, 25 Aug 2016 14:01:51 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 IN_IX_MANITU=4.35 (only DNSBL check requested) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by theia.denx.de (Postfix) with ESMTPS id 2CA0B4A039 for ; Thu, 25 Aug 2016 14:01:46 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u7PC1eEw001865; Thu, 25 Aug 2016 21:01:40 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u7PC1eEw001865 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1472126501; bh=R0hCTyBlb4QDYhWLoyJ8ANOo8s3lqjGk57d+nB2ShJc=; h=From:To:Cc:Subject:Date:From; b=vBcKV3jWKfWHfcKRG4n71oMszE+5xR5fahE8YNJtVm9FXmeZWP75upFtfp8RL/Jqv 16Cpz+qZvDz0UWagI+KWLL55wr8stpN/tGe8OzI67UgAYu9mXLTCNgPe4hKlMlMe11 cWLrM9L+IaBKULsaF2mn1OKrf81Zt4vPbpuTdodZhHlRR6+WmyTN1HLYgSPW8Y4tcp gyZFqJseaoQiCxMi7CSSWbLhzhcVgRfEsRJjfWvHe2fn9kH7hkOYfr8cVcaUl7A61s EjInBNVhUnzjmuVM1i8pOn9KoHhluvq3PdjRTThFHdbbqgqQHjoB0CxIbwND/+TZCn UKjFykyn6+O0w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 25 Aug 2016 21:03:41 +0900 Message-Id: <1472126621-12929-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH] ARM: uniphier: support system reset functionality for PSCI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This supports the system reset via PSCI for ARMv7 SoCs. Because the system reset is not supported on PSCI 0.1, let's define CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there is no CONFIG to enable it in U-Boot for now.) Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/psci.c | 5 +++++ arch/arm/mach-uniphier/reset.c | 10 +++++++++- include/configs/uniphier.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index 633a3e0..e668265 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -151,3 +151,8 @@ int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point) return PSCI_RET_SUCCESS; } + +void __secure psci_system_reset(u32 function_id) +{ + reset_cpu(0); +} diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index b5825bc..af5ad14 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -6,10 +6,18 @@ #include #include +#include #include "sc-regs.h" -void reset_cpu(unsigned long ignored) +/* If PSCI is enabled, this is used for SYSTEM_RESET function */ +#ifdef CONFIG_ARMV7_PSCI +#define __SECURE __secure +#else +#define __SECURE +#endif + +void __SECURE reset_cpu(unsigned long ignored) { u32 tmp; diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 0f5b20f..184704b 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -12,6 +12,7 @@ #define __CONFIG_UNIPHIER_COMMON_H__ #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_NR_CPUS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10