From patchwork Tue Aug 30 07:22:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 74950 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp2001895qga; Tue, 30 Aug 2016 00:21:17 -0700 (PDT) X-Received: by 10.28.198.6 with SMTP id w6mr13390924wmf.63.1472541677144; Tue, 30 Aug 2016 00:21:17 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id u4si36597819wjz.161.2016.08.30.00.21.16; Tue, 30 Aug 2016 00:21:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0D878A7594; Tue, 30 Aug 2016 09:21:13 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bAPlXUYQXNzJ; Tue, 30 Aug 2016 09:21:12 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E6CCA754C; Tue, 30 Aug 2016 09:21:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 747A0A7576 for ; Tue, 30 Aug 2016 09:21:09 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MoJ0OA5Bz68q for ; Tue, 30 Aug 2016 09:21:09 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by theia.denx.de (Postfix) with ESMTPS id BFC73A7528 for ; Tue, 30 Aug 2016 09:21:08 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id u7U7KFsi016675; Tue, 30 Aug 2016 16:20:20 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com u7U7KFsi016675 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1472541621; bh=Q5zNvSxmQiVAq4rY4B258DyozGD3wgCEZaY7i0ZDjlg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ehMuOHCMKpfmS+/z8ooinnpLQ0Tg6FVdPVCXRa0wcYeHjuY0cJAB+bYdSv96GljNs UjfdDS2ByODyTgXIevI5bspXED5flcL1k9Qc7scLLYpLGRJ6c5roa/VGQiL6OZS2mG pBVYgPGA3I5lHdWK4ThfrTL/un0ufFiSXx1l5ih47/evDixQ39qAfq9ALnEFVwiM21 FnHuq+t65XxSRCEL96EMnPJrW0sKIbLW7iz9HyYrmCrEhUmdRmnmdhVo+3vwHmkxi6 CPK2delst1KTucHe4FTILwncMvflj0/NucxpfYSAP1HHJDk0E9aDS7+dOLwF65R+hw 1Q/GBg0BF3Weg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 30 Aug 2016 16:22:23 +0900 Message-Id: <1472541743-18717-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472541743-18717-1-git-send-email-yamada.masahiro@socionext.com> References: <1472541743-18717-1-git-send-email-yamada.masahiro@socionext.com> Cc: Chander Kashyap , Steve Rae , Stefan Agner , Alison Wang , Stephen Warren , Ian Campbell , Fabio Estevam Subject: [U-Boot] [PATCH v2 4/4] ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move this option to Kconfig and set its default value to 4; this increases the number of supported CPUs for some boards. It consumes 1KB memory per CPU for PSCI stack, but it should not be a big deal, given the amount of memory used for the modern OSes. Signed-off-by: Masahiro Yamada --- Changes in v2: - Add help to the Kconfig entry arch/arm/cpu/armv7/Kconfig | 9 +++++++++ include/configs/arndale.h | 1 - include/configs/bcm_ep_board.h | 1 - include/configs/jetson-tk1.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/mx7_common.h | 1 - include/configs/sun6i.h | 1 - include/configs/sun7i.h | 1 - include/configs/sun8i.h | 12 ------------ include/configs/uniphier.h | 1 - include/configs/vexpress_ca15_tc2.h | 1 - 12 files changed, 9 insertions(+), 22 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 4390f59..b9c4f4e 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -41,6 +41,15 @@ config ARMV7_PSCI help Say Y here to enable PSCI support. +config ARMV7_PSCI_NR_CPUS + int "Maximum supported CPUs for PSCI" + depends on ARMV7_NONSEC + default 4 + help + The maximum number of CPUs supported in the PSCI firmware. + It is no problem to set a larger value than the number of + CPUs in the actual hardware implementation. + config ARMV7_LPAE bool "Use LPAE page table format" if EXPERT depends on CPU_V7 diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 18e59fc..b08f341 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -45,7 +45,6 @@ #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index b5e5029..4b255d8 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -91,6 +91,5 @@ /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER #define CONFIG_CRC32_VERIFY -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 1eba74a..7c59790 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -60,7 +60,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 86969a1..abbd1c4 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,7 +10,6 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d0fc7ff..511b0b3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -10,7 +10,6 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 52c0d0f..4b1077c 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -72,7 +72,6 @@ #define CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP -#define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE 0x00900000 #endif diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 41552c4..67a26c2 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -22,7 +22,6 @@ #define CONFIG_SUNXI_USB_PHYS 3 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 63760c5..d8e6e20 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -20,7 +20,6 @@ #define CONFIG_SUNXI_USB_PHYS 3 -#define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 151ffdc..011d70f 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -26,18 +26,6 @@ #define CONFIG_SUNXI_USB_PHYS 2 #endif -#ifndef CONFIG_MACH_SUN8I_A83T -#if defined(CONFIG_MACH_SUN8I_A23) -#define CONFIG_ARMV7_PSCI_NR_CPUS 2 -#elif defined(CONFIG_MACH_SUN8I_A33) -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 -#elif defined(CONFIG_MACH_SUN8I_H3) -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 -#else -#error Unsupported sun8i variant -#endif -#endif - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 66696c2..b3ca46b 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -12,7 +12,6 @@ #define __CONFIG_UNIPHIER_COMMON_H__ #define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 9583e8c..b509a9c 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -16,6 +16,5 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #endif