From patchwork Fri Jan 20 09:30:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 92047 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp691760qgi; Fri, 20 Jan 2017 01:31:58 -0800 (PST) X-Received: by 10.223.131.34 with SMTP id 31mr13140256wrd.119.1484904718261; Fri, 20 Jan 2017 01:31:58 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id 6si7240597wrz.292.2017.01.20.01.31.56; Fri, 20 Jan 2017 01:31:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 995FC4AAA7; Fri, 20 Jan 2017 10:31:55 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jdScq5Q9KzAu; Fri, 20 Jan 2017 10:31:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D96D24A9D6; Fri, 20 Jan 2017 10:31:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F23674A9D6 for ; Fri, 20 Jan 2017 10:31:50 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YGWP2JWsnrRW for ; Fri, 20 Jan 2017 10:31:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by theia.denx.de (Postfix) with ESMTPS id 3E3FC4A99B for ; Fri, 20 Jan 2017 10:31:46 +0100 (CET) Received: from pug.jp.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id v0K9V12o002599; Fri, 20 Jan 2017 18:31:02 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v0K9V12o002599 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1484904662; bh=VNfpClAw0HSKXjB+UK1Ti0vnaalsuYGJb++CI20gOxI=; h=From:To:Cc:Subject:Date:From; b=viTCIc2aGGS85N4b31DsiYxW5LKs8g0v2EvXk8fFeHz2f4voUTeJj0TUCCqy04KVF sQSALtd/FPV1TtMI+Co/rKwT+57v+MvPnnt9YvqCiCA8Gzyojwni/E1Tu3NU8IgGjO j1z/sc2gK39PX2SP3gCj/zy2sHiJ/rIgrssdfiQZBPFizVxD1t8kUD+V6mnoLhw+3B xgV4TaOJi+GQHnXjtM680HG3wfuqzX3aZ6xVc5iF0oq+Imkjyc46dQmWW0AOJ7rKhP bkjDY2RAJZAuzo5bgUDL3W/4LDBSo7HRQTnogjN+dL1lZjitq7ujVl7Tqu7uGRZuKy kThsjGch1+KkQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 20 Jan 2017 18:30:58 +0900 Message-Id: <1484904658-31540-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Cc: Tom Rini , Marek Vasut , Stefan Agner , Michal Simek Subject: [U-Boot] [PATCH] Revert "armv8: release slave cores from CPU_RELEASE_ADDR" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This reverts commit 8c36e99f211104fd7dcbf0669a35a47ce5e154f5. There is misunderstanding in commit 8c36e99f2111 ("armv8: release slave cores from CPU_RELEASE_ADDR"). How to bring the slave cores into U-Boot proper is platform-specific. So, it should be cared in SoC/board files instead of common/spl/spl.c. As you see SPL is the acronym of Secondary Program Loader, there is generally something that runs before SPL (the First one is usually Boot ROM). How to wake up slave cores from the Boot ROM is really SoC specific. So, the intention for the spin table support is to bring the slave cores into U-Boot proper in an SoC specific manner. (this must be done after relocation. see below.) If you bring the slaves into SPL, it is SoC own code responsibility to transfer them to U-Boot proper. The Spin Table defines the interface between a boot-loader and Linux kernel. It is unrelated to the interface between SPL and U-Boot proper. One more thing is missing in the commit; spl_image->entry_point points to the entry address of U-Boot *before* relocation. U-Boot relocates itself between board_init_f() and board_init_r(). This means the master CPU sees the different copy of the spin code than the slave CPUs enter. The spin_table_update_dt() protects the code *after* relocation. As a result, the slave CPUs spin in unprotected code, which leads to unstable behavior. Signed-off-by: Masahiro Yamada --- common/spl/spl.c | 8 -------- 1 file changed, 8 deletions(-) -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Reviewed-by: Simon Glass diff --git a/common/spl/spl.c b/common/spl/spl.c index 8fb8da4..d3a4ff6 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -167,14 +167,6 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) (image_entry_noargs_t)spl_image->entry_point; debug("image entry point: 0x%lX\n", spl_image->entry_point); -#if defined(CONFIG_ARMV8_SPIN_TABLE) && defined(CONFIG_ARMV8_MULTIENTRY) - /* - * Release all slave cores from CPU_RELEASE_ADDR so they could - * arrive to the spin-table code in start.S of the u-boot - */ - *(ulong *)CPU_RELEASE_ADDR = (ulong)spl_image->entry_point; -#endif - image_entry(); }