From patchwork Thu Sep 28 12:13:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 114415 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp664624qgf; Thu, 28 Sep 2017 05:13:43 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAQXhwwcUYUHrf9ROQT+EsKOlVDeqqBpC2R7QB9EM7fMBx/W2bzrLou1DhxIssWs3WtlrqH X-Received: by 10.80.215.206 with SMTP id m14mr5428035edj.81.1506600823617; Thu, 28 Sep 2017 05:13:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506600823; cv=none; d=google.com; s=arc-20160816; b=u3ZW661G5V1pgf+/ORaraGxTVc8s1nv0ETNYXEidsDojtfUHg1yunGsPTjQaog/mR2 c3v8HWPWCwUjwyt34/gd11UYXgPcJd3NbcOXplzUg2I5/fCpd5AtPC0UjXXFL0/DoDAT KjBwt4Jr/+1DaZqDQ3rDo7ItDaB/OD2RZNeHAcFyfRAut0rnfdNKq92Si2WXuQePC6cq 3wSa9TudUHeUCaRS+GwHqdC0PJWQGVvH5kLaQBCIlP8Pj2eD7tHk3el203Xi1UdoBExA ItG8HV3q4FTyn3RT6Q5r4xnCtV2vP76TaKV9pit96ZSOOz4T0FjabATCTaghtcCvyKqG S9RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :dkim-filter:arc-authentication-results; bh=lUFMpS6Ku/5IxhxdEpFNpaEPJGO3h86TO57yZSNyPvA=; b=x0tvIqHBrrYQcFaqbw8lOVDQDo5jy5E4D3n9ANS93KiFacE3A4JRxpfRkt+xMD5rc3 VDFdgfOg9Xks/imraWCNiXYdx7coSnrsRz5k7um/5unTKJmkuS7ZYnHq1gUkKCxYNeww hRnNbZRt76W9NQJKAiomkJ+lgJw41cPNhka2XjIP6wp3n/nLua+Y+lUf84pmpzQysiin 1bYCxvhybqeFeCNo6X01QziqY2wYyM+DwEdnTXBldAavxLTWBsqG7nO+bErs6Ji3C9ZA e4qyD7w61APFmDv9yY6TYJJiE0fwpcwKT5q3q7zYdjisSvHKgBoPqqxknJw3z4SNcSay cLEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=d8So/V1I; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 7si1613046edf.105.2017.09.28.05.13.42; Thu, 28 Sep 2017 05:13:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=d8So/V1I; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 5F672C21DD9; Thu, 28 Sep 2017 12:13:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 13840C21D09; Thu, 28 Sep 2017 12:13:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BDA31C21D09; Thu, 28 Sep 2017 12:13:34 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id BC269C21CB1 for ; Thu, 28 Sep 2017 12:13:33 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v8SCDESK017436; Thu, 28 Sep 2017 21:13:14 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v8SCDESK017436 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506600795; bh=RUkUuoIgnO9TTj0yT5BnLSa5K0K9niOTCXIAboG7lgI=; h=From:To:Cc:Subject:Date:From; b=d8So/V1IKmmZyU3ATWjIuKFSRr7HIy5vnB8XIJPWsY13uHVLCZlI4ppNoQ7PFftaT UQm6oXxqvuq8j/6YuC8d5TIqI3YQ52UERUeyHetIrTVi+ttsBdfo+uyQQyZOACsuFr NVNtdjwUq7YdSps0VAEGNF4RU8PbEffgdvbnCqzRlmlWzUjqeuT5bbbBuZzrRRtOXC DXEH4/cbdYK4lk5yA2OkyvipyeuKCkb+VRIiJMk8HbKyBVIoYN28EJC7tABFVA3G86 NhFZ60X4mS5iDUfl6lpysWh41V46pv0rj+2Egf1coEn+6rGpvDzTm5hSYBauml+Ti0 50No00aK8z4gA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 28 Sep 2017 21:13:10 +0900 Message-Id: <1506600790-29419-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] mmc: sdhci-cadence: set timing mode register depending on frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The MMC framework in U-Boot does not support a systematic API for timing switch like mmc_set_timing() in Linux. U-Boot just provides a hook to change the clock frequency via mmc_set_clock(). It is up to drivers if additional register settings are needed. This driver needs to set a correct timing mode into a register when it migrates to a different speed mode. Only increasing clock frequency could result in setup/hold timing violation. The timing mode should be decided by checking MMC_TIMING_* like drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not supported by U-Boot for now. Just use mmc->clock to decide the timing mode. Signed-off-by: Masahiro Yamada --- This is a repost. I sent the same one before http://patchwork.ozlabs.org/patch/764647/ I retracted it because I saw amazing framework improvements for MMC. 4 months have passed since then, but nothing happened. I do not wait any more. I am reposting it. drivers/mmc/sdhci-cadence.c | 51 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index f83c1d7..72d1c64 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -23,6 +23,18 @@ #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 +#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f +#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 + /* SRS - Slot Register Set (SDHCI-compatible) */ #define SDHCI_CDNS_SRS_BASE 0x200 @@ -111,6 +123,44 @@ static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, return 0; } +static void sdhci_cdns_set_control_reg(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev); + unsigned int clock = mmc->clock; + u32 mode, tmp; + + /* + * REVISIT: + * The mode should be decided by MMC_TIMING_* like Linux, but + * U-Boot does not support timing. Use the clock frequency instead. + */ + if (clock <= 26000000) + mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */ + else if (clock <= 52000000) { + if (mmc->ddr_mode) + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; + else + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; + } else { + /* + * REVISIT: + * The IP supports HS200/HS400, revisit once U-Boot support it + */ + printf("unsupported frequency %d\n", clock); + return; + } + + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); + tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; + tmp |= mode; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); +} + +static const struct sdhci_ops sdhci_cdns_ops = { + .set_control_reg = sdhci_cdns_set_control_reg, +}; + static int sdhci_cdns_bind(struct udevice *dev) { struct sdhci_cdns_plat *plat = dev_get_platdata(dev); @@ -137,6 +187,7 @@ static int sdhci_cdns_probe(struct udevice *dev) host->name = dev->name; host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; + host->ops = &sdhci_cdns_ops; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));