From patchwork Thu Oct 26 12:24:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 117206 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp700412qgn; Thu, 26 Oct 2017 05:25:19 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Ro2nYDHtd/MvkKQgr97Na7kfFFXJf3qMIMVTJ4Nlk1+9ym5/CkLI833o4pwbAUmHtluTq7 X-Received: by 10.80.131.230 with SMTP id 93mr27334162edi.12.1509020719147; Thu, 26 Oct 2017 05:25:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509020719; cv=none; d=google.com; s=arc-20160816; b=LQ8qrI9TDbPbTIoar9tHLrrOlrs4SlDBprI0csJpabCdC4FdIRu0ujbrNWaG1xcG0e 4n8EiTiN5jhCKFB8zljHxsF8brzafqdw4jQytlkZ6SuTalL5LNIFNhpojoIF0iuXd3DF FgOqHhjBpujKsO4upZZOslQA48BSFlKZsPs1aosMWUAxWa+9fmpU4WZ5kuLjQfGs/hjk OW2PdT91XWu5KDY9yaXL/QXTNZBygKmn6D5fSRfzghe9WJlgdp3OzJm0cxaOx54dP8hJ DfMNsyOhTO6f2uXK/CLgWSmxH/sN9m81QhB9Gi5BdqHd9l+WpTh0kvkY5k3NNvjFEXJQ wK7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=GqT8ZGzas2b+JUyh00KaT53MXZzYdF5CzUf9w9kkKDU=; b=DC9+kluJgLWhAj4/KwNtxsjlaZHkI0oylaLNOfcNYcaPYfpXMu4lhpvQTrAHh8k8TN gEXBA711mys/oO2ZFiGbws+gYX0cYEeJ2djm+PdgiXWdmquLNf3eFST4TWwhr6hucCAb DjFW0vQfA+d9bQMznxOjQ4uVGT0sSslali+Cbxzy2ph8gb8q/Ht8ewNKHTRdHSM+if5e 8kggup4cDjqdoGpGfWXz1ZcVFC798caajGs3iI5h0hJRwhRPATYn5CpjIhBobTSz/fg4 asD9L8ThqEe/B4vl0gHeWxX+vUk4Joi6JR4wQkjApnvMzHqzq5cTRaMUNjUnU8ZNOz2C qG4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=QH/BU1v2; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id f15si3683378edb.205.2017.10.26.05.25.18; Thu, 26 Oct 2017 05:25:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=QH/BU1v2; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 3DF67C21DEF; Thu, 26 Oct 2017 12:25:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5E2E9C21C73; Thu, 26 Oct 2017 12:25:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5C09DC21D84; Thu, 26 Oct 2017 12:25:12 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 425F2C21C73 for ; Thu, 26 Oct 2017 12:25:10 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v9QCOle7008415; Thu, 26 Oct 2017 21:24:51 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v9QCOle7008415 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1509020691; bh=RTWwmGGrchbYjMJQvlhKn6p+5TSDmvPh5kmhDeibLBQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QH/BU1v2ZYxjiHVNgz9qvAXSLgF6rdqdef4JKiK0SiDuScH1z/27ivBndnVNX1dyf yvxU69Ypa3BCtvCYeH8ZlsYvfPi1ITN5SesY9R3GHnesCyf+7d+FEKqmrIzBWNBs0o dXXIiZglzNihEsMEkaosgxz5mFdTiWKlS8VcM1psP91ifV9Yn5PirmfjSl8ZfbHXal nimjDfXgeXU2B8x4tihsQeQKPoglauZ7jZRUSYt05uFwpuD9hMEeLVtBVehbFXRQTJ mOScHmDLl0K+q2rsOkc2WnVOQGPDfqAtRxb6oPD1Is3Xj5dRNUQjwPBOvFZEu+TcBg t8xvsy5OllCDQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 26 Oct 2017 21:24:16 +0900 Message-Id: <1509020671-1321-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509020671-1321-1-git-send-email-yamada.masahiro@socionext.com> References: <1509020671-1321-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 01/16] i2c: adi_i2c: remove left-over Blackfin I2C driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver was used by Blackfin boards, but Blackfin support is gone. There is no user of this driver. Signed-off-by: Masahiro Yamada Acked-by: Heiko Schocher --- drivers/i2c/Makefile | 1 - drivers/i2c/adi_i2c.c | 309 -------------------------------------------------- 2 files changed, 310 deletions(-) delete mode 100644 drivers/i2c/adi_i2c.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index e7ade94..121e4e2 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o -obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c deleted file mode 100644 index d340639..0000000 --- a/drivers/i2c/adi_i2c.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * i2c.c - driver for ADI TWI/I2C - * - * Copyright (c) 2006-2014 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include -#include -#include - -#include -#include -#include - -static struct twi_regs *i2c_get_base(struct i2c_adapter *adap); - -/* Every register is 32bit aligned, but only 16bits in size */ -#define ureg(name) u16 name; u16 __pad_##name; -struct twi_regs { - ureg(clkdiv); - ureg(control); - ureg(slave_ctl); - ureg(slave_stat); - ureg(slave_addr); - ureg(master_ctl); - ureg(master_stat); - ureg(master_addr); - ureg(int_stat); - ureg(int_mask); - ureg(fifo_ctl); - ureg(fifo_stat); - char __pad[0x50]; - ureg(xmt_data8); - ureg(xmt_data16); - ureg(rcv_data8); - ureg(rcv_data16); -}; -#undef ureg - -#ifdef TWI_CLKDIV -#define TWI0_CLKDIV TWI_CLKDIV -# ifdef CONFIG_SYS_MAX_I2C_BUS -# undef CONFIG_SYS_MAX_I2C_BUS -# endif -#define CONFIG_SYS_MAX_I2C_BUS 1 -#endif - -/* - * The way speed is changed into duty often results in integer truncation - * with 50% duty, so we'll force rounding up to the next duty by adding 1 - * to the max. In practice this will get us a speed of something like - * 385 KHz. The other limit is easy to handle as it is only 8 bits. - */ -#define I2C_SPEED_MAX 400000 -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) -#define I2C_DUTY_MIN 0xff /* 8 bit limited */ -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) -/* Note: duty is inverse of speed, so the comparisons below are correct */ -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN -# error "The I2C hardware can only operate 20KHz - 400KHz" -#endif - -/* All transfers are described by this data structure */ -struct adi_i2c_msg { - u8 flags; -#define I2C_M_COMBO 0x4 -#define I2C_M_STOP 0x2 -#define I2C_M_READ 0x1 - int len; /* msg length */ - u8 *buf; /* pointer to msg data */ - int alen; /* addr length */ - u8 *abuf; /* addr buffer */ -}; - -/* Allow msec timeout per ~byte transfer */ -#define I2C_TIMEOUT 10 - -/** - * wait_for_completion - manage the actual i2c transfer - * @msg: the i2c msg - */ -static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg) -{ - u16 int_stat, ctl; - ulong timebase = get_timer(0); - - do { - int_stat = readw(&twi->int_stat); - - if (int_stat & XMTSERV) { - writew(XMTSERV, &twi->int_stat); - if (msg->alen) { - writew(*(msg->abuf++), &twi->xmt_data8); - --msg->alen; - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - writew(*(msg->buf++), &twi->xmt_data8); - --msg->len; - } else { - ctl = readw(&twi->master_ctl); - if (msg->flags & I2C_M_COMBO) - writew(ctl | RSTART | MDIR, - &twi->master_ctl); - else - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & RCVSERV) { - writew(RCVSERV, &twi->int_stat); - if (msg->len) { - *(msg->buf++) = readw(&twi->rcv_data8); - --msg->len; - } else if (msg->flags & I2C_M_STOP) { - ctl = readw(&twi->master_ctl); - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & MERR) { - writew(MERR, &twi->int_stat); - return msg->len; - } - if (int_stat & MCOMP) { - writew(MCOMP, &twi->int_stat); - if (msg->flags & I2C_M_COMBO && msg->len) { - ctl = readw(&twi->master_ctl); - ctl = (ctl & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR; - writew(ctl, &twi->master_ctl); - } else - break; - } - - /* If we were able to do something, reset timeout */ - if (int_stat) - timebase = get_timer(0); - - } while (get_timer(timebase) < I2C_TIMEOUT); - - return msg->len; -} - -static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr, - int alen, uint8_t *buffer, int len, uint8_t flags) -{ - struct twi_regs *twi = i2c_get_base(adap); - int ret; - u16 ctl; - uchar addr_buffer[] = { - (addr >> 0), - (addr >> 8), - (addr >> 16), - }; - struct adi_i2c_msg msg = { - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), - .buf = buffer, - .len = len, - .abuf = addr_buffer, - .alen = alen, - }; - - /* wait for things to settle */ - while (readw(&twi->master_stat) & BUSBUSY) - if (ctrlc()) - return 1; - - /* Set Transmit device address */ - writew(chip, &twi->master_addr); - - /* Clear the FIFO before starting things */ - writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); - writew(0, &twi->fifo_ctl); - - /* prime the pump */ - if (msg.alen) { - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; - writew(*(msg.abuf++), &twi->xmt_data8); - --msg.alen; - } else if (!(msg.flags & I2C_M_READ) && msg.len) { - writew(*(msg.buf++), &twi->xmt_data8); - --msg.len; - } - - /* clear int stat */ - writew(-1, &twi->master_stat); - writew(-1, &twi->int_stat); - writew(0, &twi->int_mask); - - /* Master enable */ - ctl = readw(&twi->master_ctl); - ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - writew(ctl, &twi->master_ctl); - - /* process the rest */ - ret = wait_for_completion(twi, &msg); - - if (ret) { - ctl = readw(&twi->master_ctl) & ~MEN; - writew(ctl, &twi->master_ctl); - ctl = readw(&twi->control) & ~TWI_ENA; - writew(ctl, &twi->control); - ctl = readw(&twi->control) | TWI_ENA; - writew(ctl, &twi->control); - } - - return ret; -} - -static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed) -{ - struct twi_regs *twi = i2c_get_base(adap); - u16 clkdiv = I2C_SPEED_TO_DUTY(speed); - - /* Set TWI interface clock */ - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) - return -1; - clkdiv = (clkdiv << 8) | (clkdiv & 0xff); - writew(clkdiv, &twi->clkdiv); - - /* Don't turn it on */ - writew(speed > 100000 ? FAST : 0, &twi->master_ctl); - - return 0; -} - -static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - struct twi_regs *twi = i2c_get_base(adap); - u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; - - /* Set TWI internal clock as 10MHz */ - writew(prescale, &twi->control); - - /* Set TWI interface clock as specified */ - i2c_set_bus_speed(speed); - - /* Enable it */ - writew(TWI_ENA | prescale, &twi->control); -} - -static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, uint8_t *buffer, int len) -{ - return i2c_transfer(adap, chip, addr, alen, buffer, - len, alen ? I2C_M_COMBO : I2C_M_READ); -} - -static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, uint8_t *buffer, int len) -{ - return i2c_transfer(adap, chip, addr, alen, buffer, len, 0); -} - -static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip) -{ - u8 byte; - return adi_i2c_read(adap, chip, 0, 0, &byte, 1); -} - -static struct twi_regs *i2c_get_base(struct i2c_adapter *adap) -{ - switch (adap->hwadapnr) { -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: - return (struct twi_regs *)TWI2_CLKDIV; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: - return (struct twi_regs *)TWI1_CLKDIV; -#endif - case 0: - return (struct twi_regs *)TWI0_CLKDIV; - - default: - printf("wrong hwadapnr: %d\n", adap->hwadapnr); - } - - return NULL; -} - -U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe, - adi_i2c_read, adi_i2c_write, - adi_i2c_setspeed, - CONFIG_SYS_I2C_SPEED, - 0, - 0) - -#if CONFIG_SYS_MAX_I2C_BUS > 1 -U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe, - adi_i2c_read, adi_i2c_write, - adi_i2c_setspeed, - CONFIG_SYS_I2C_SPEED, - 0, - 1) -#endif - -#if CONFIG_SYS_MAX_I2C_BUS > 2 -U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe, - adi_i2c_read, adi_i2c_write, - adi_i2c_setspeed, - CONFIG_SYS_I2C_SPEED, - 0, - 2) -#endif