From patchwork Tue Nov 21 17:38:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 119379 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5572759qgn; Tue, 21 Nov 2017 09:45:44 -0800 (PST) X-Google-Smtp-Source: AGs4zMaXRoBbpMW7dxch/us7i2Z3GXghfooIdkSv4/bRkC6m/0GuU0D520zAcyjrJYDT4dRHShoP X-Received: by 10.80.148.199 with SMTP id t7mr25593470eda.124.1511286344208; Tue, 21 Nov 2017 09:45:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511286344; cv=none; d=google.com; s=arc-20160816; b=YOKhz422Odnx1jgWGwCLuFd4/aQAFYpRGpapxqBqWV6uS8BPuFcVWlR94a8lzCKXST tsQfwEH3YtZ9v30DTp/AMi9bur3DeRIT8waabwyJJHcn2MyaoSAdh1byLtdVmlyrQOpX xdWE7GO+qZQU9YnSO3CMryIoSYt3mSce3B+fPo8YaQ+JDFeuamEhGUQPCSqzhz2M6vAR MuM50X7Y+vj05vWi0U80PecNspccqoaxf75xFIYx2MtPjGeqnLHnJGwIGFty8+NnSUw0 nS0x6qPsm/ia7zB8RnBHfumH8zJjZic84Mk4YEO2vvo9CvHceE8Grq4nWoDwWh9c1Vcn ePkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=QASUEzVjHG+qIsgIE2CTTG2bw8OLPRqFpT0kukdV+vE=; b=i72pC1Mc/Zp17wT8oYs8sVwNWYfpy8bgOhXtwnPeHXE6aXGz9COCgaZb/U8VbpkiWB 3UOKQn3SeNv4ZyEdvjL5QVS0m2bOUVdzZtnYnVwLBIND74bzU04+kLUyJc5O3FTSqD70 7aGloB3e1KD9M2QZvFrSFJFvTWIVMX8KDSMTg4/vXzQMUjmfwY+glJaixc7bRiwlOJfv g67jgkIUmjywLY/JBgOEz1C0fX0jkNWuw9ljkh52ruH7hPaDupMTGicKBHcKin7/HEko ijSm+a0/0e07WnMd7pzSrLMEk0aJwf+5+tnRpm42kQcY2IujhKxiOb4QqehWeA85MwGY ekjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=srsHDine; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 5si861041edj.439.2017.11.21.09.45.43; Tue, 21 Nov 2017 09:45:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=srsHDine; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 9F766C21F92; Tue, 21 Nov 2017 17:41:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D14E8C21DDF; Tue, 21 Nov 2017 17:39:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 85330C21DF1; Tue, 21 Nov 2017 17:39:07 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id 47C78C21F5E for ; Tue, 21 Nov 2017 17:39:04 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-07.nifty.com with ESMTP id vALHcbu0001225; Wed, 22 Nov 2017 02:38:42 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com vALHcbu0001225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1511285922; bh=Qnghw3e/aQA1o/H7OJ+SHKJCeRsCHLwtL36uQwp8P20=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=srsHDinehWGb5V2VpvyFbwIjEaDxmCpct9PnQEzYlQtyytL2DvWYdaU5lgOzklOtj 1PNI/5OfNnFbtGdvXz6lC5TW0dk/3/qx+qdEil1Ruutd3uzCJEtAB5BRIdTSn9fLwY hXTWMMq9bLjFshJpPuIjcI9V+Yom0nsGfYQDjgnmFANKEWnDyOFn+odEnU/8Mo38Up /kThMcNe6aS/2lcILI90mdfm9/eaShemypJ++ikSpDiqHns2CscPyFV2DsI7Nb7Z6h YyK0+yTXk79A3gLGit96ZLakxBeNJpE2qogpWFd3aSdg2/gyEEguo39M3jrjeCr0p5 jE+y/jp9xRqZQ== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 22 Nov 2017 02:38:20 +0900 Message-Id: <1511285912-12452-11-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> References: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood Subject: [U-Boot] [PATCH 10/22] mtd: nand: Fix data interface configuration logic X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Boris Brezillon When changing from one data interface setting to another, one has to ensure a specific sequence which is described in the ONFI spec. One of these constraints is that the CE line has go high after a reset before a command can be sent with the new data interface setting, which is not guaranteed by the current implementation. Rework the nand_reset() function and all the call sites to make sure the CE line is asserted and released when required. Also make sure to actually apply the new data interface setting on the first die. Signed-off-by: Boris Brezillon Fixes: d8e725dd8311 ("mtd: nand: automate NAND timings selection") Reviewed-by: Sascha Hauer Tested-by: Marc Gonzalez [Linux commit: 73f907fd5fa56b0066d199bdd7126bbd04f6cd7b] Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/nand_base.c | 48 +++++++++++++++++++++++++++++++++----------- include/linux/mtd/nand.h | 2 +- 2 files changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index f452f59..5054c0e 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1046,10 +1046,11 @@ static void __maybe_unused nand_release_data_interface(struct nand_chip *chip) /** * nand_reset - Reset and initialize a NAND device * @chip: The NAND chip + * @chipnr: Internal die id * * Returns 0 for success or negative error code otherwise */ -int nand_reset(struct nand_chip *chip) +int nand_reset(struct nand_chip *chip, int chipnr) { struct mtd_info *mtd = nand_to_mtd(chip); int ret; @@ -1058,9 +1059,17 @@ int nand_reset(struct nand_chip *chip) if (ret) return ret; + /* + * The CS line has to be released before we can apply the new NAND + * interface settings, hence this weird ->select_chip() dance. + */ + chip->select_chip(mtd, chipnr); chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + chip->select_chip(mtd, -1); + chip->select_chip(mtd, chipnr); ret = nand_setup_data_interface(chip); + chip->select_chip(mtd, -1); if (ret) return ret; @@ -2746,10 +2755,6 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, } chipnr = (int)(to >> chip->chip_shift); - chip->select_chip(mtd, chipnr); - - /* Shift to get page */ - page = (int)(to >> chip->page_shift); /* * Reset the chip. Some chips (like the Toshiba TC5832DC found in one @@ -2757,7 +2762,12 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, * if we don't do this. I have no clue why, but I seem to have 'fixed' * it in the doc2000 driver in August 1999. dwmw2. */ - nand_reset(chip); + nand_reset(chip, chipnr); + + chip->select_chip(mtd, chipnr); + + /* Shift to get page */ + page = (int)(to >> chip->page_shift); /* Check, if it is write protected */ if (nand_check_wp(mtd)) { @@ -3771,14 +3781,14 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, int i, maf_idx; u8 id_data[8]; - /* Select the device */ - chip->select_chip(mtd, 0); - /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) * after power-up. */ - nand_reset(chip); + nand_reset(chip, 0); + + /* Select the device */ + chip->select_chip(mtd, 0); /* Send the command for reading device ID */ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); @@ -4033,17 +4043,31 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, return PTR_ERR(type); } + /* Initialize the ->data_interface field. */ ret = nand_init_data_interface(chip); if (ret) return ret; + /* + * Setup the data interface correctly on the chip and controller side. + * This explicit call to nand_setup_data_interface() is only required + * for the first die, because nand_reset() has been called before + * ->data_interface and ->default_onfi_timing_mode were set. + * For the other dies, nand_reset() will automatically switch to the + * best mode for us. + */ + ret = nand_setup_data_interface(chip); + if (ret) + return ret; + chip->select_chip(mtd, -1); /* Check for a chip array */ for (i = 1; i < maxchips; i++) { - chip->select_chip(mtd, i); /* See comment in nand_get_flash_type for reset */ - nand_reset(chip); + nand_reset(chip, i); + + chip->select_chip(mtd, i); /* Send the command for reading device ID */ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 274bd8d..8cff83b 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -1198,6 +1198,6 @@ int nand_check_erased_ecc_chunk(void *data, int datalen, int threshold); /* Reset and initialize a NAND device */ -int nand_reset(struct nand_chip *chip); +int nand_reset(struct nand_chip *chip, int chipnr); #endif /* __LINUX_MTD_NAND_H */