From patchwork Fri Dec 29 17:00:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 122948 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4919004qgn; Fri, 29 Dec 2017 09:06:42 -0800 (PST) X-Google-Smtp-Source: ACJfBotwzZxp4t4LAougIhTr1F8IdPSc4oFE3DnR/ESRJr8wBFz+egmmXT2oQHBWE+137GGV+YCn X-Received: by 10.80.164.87 with SMTP id v23mr44590855edb.99.1514567202857; Fri, 29 Dec 2017 09:06:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1514567202; cv=none; d=google.com; s=arc-20160816; b=RfItupT5qx0o8I0V+FREOeaYg4tvcQDOhbAMoGN08f3tZmZSb0wMyLLDxHqd0rQ2f9 VrKUdygb01fijcaY5ukD/9u/QHAnp02UWHhZi642+JnjuHZyPKqC9AG32mhtcGvdjoAu Cc6/MwUsKBkWUKJZc6thFvy9qHG8KTUxTNKkR/YmYQqXIB+msr4Is/4NRgX8VHuDvuAA O2LbzrQH0nGzYHJ5lZL6O0Bs8xEhXc5AweQ8pTL6w19bwjUtwVwVX7WLrGVHWeSrVB6V 6p7I/Zn9vQWOjdpr56zupHVDlm8sabOVYHIBwhZT0KsVQiadyZJ5MvnKf8HgzNp+gIbf 4rIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=Zin3cxkcliu7CC/Fi2a8RtHP4rkQsYLVIlyL40DDrmc=; b=ig2DMjQZHScgaZIo4H36VkRtC69jIJQGBZNcC3JqW+3FT+lY/uU0eLp5EIq6XtBy7o k6+zXWfOYUkaaQKrqa+Q8IaJpjH6ViKfAI/Vtazuz39E1t29SUthYhhrQ9zfl3rkbJKR 9uEqk2JhYUGyU5lujhg3igZsaKLVSOAbPoIm/v2wz7rq/q9DARU2Z6yNM1fCfvZ5BzfP IpIPbKmshgnzn5WoVlfqFY1Cj3VorMoiXq9j7cNlzy/p9m0b+JD/dM1Q/nGMb+3mFMn3 XaWXMq02JAEdO35KZqDczx/UYe/kGRaSHX2HTYUbJAWHM1WwHTXv6gaMCLJZBOlGAGl4 1XAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=L5wLpYaF; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g9si8745859edi.196.2017.12.29.09.06.42; Fri, 29 Dec 2017 09:06:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=L5wLpYaF; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 76EBCC21DD9; Fri, 29 Dec 2017 17:02:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 280D2C21E09; Fri, 29 Dec 2017 17:00:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A87D1C21C59; Fri, 29 Dec 2017 17:00:39 +0000 (UTC) Received: from conuserg-08.nifty.com (conuserg-08.nifty.com [210.131.2.75]) by lists.denx.de (Postfix) with ESMTPS id 4B180C21D9F for ; Fri, 29 Dec 2017 17:00:38 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-08.nifty.com with ESMTP id vBTH0O9O000541; Sat, 30 Dec 2017 02:00:28 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com vBTH0O9O000541 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1514566828; bh=THeOiAUMlQIRObCnwKYKVMnD4AnYwEwG6vwvJwAG0b0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L5wLpYaF2Olc7Dz4d4vW7yy6Ps6nG6K2c+Mb8ZvkR7Eo3jwoPRYscr9hokkjsb+6Q OlezlD4Zm2gSLTF7lzEXSakBv2ol8JmlB0iFLpjEksn7BWjDsIPVSv98GZAqS+aCiL hmwJIlEutjLxgjq/GpWAvf4lcyfjINqppIWtCdyO/keWe0kAX6IzyZwNYSZmWFFrEj v1dyVDi5a03a6+O/YNHxc47VG48GPgMuSnUMNSm+kUe1ZeDUJj/n7kkqHPvfp1OQoG V/SK/U60n3mWkVmJHVzBHH5rr3+34CUGiFlrZL9xt/oP3ryywWe5YfFoEif9o9193Y whxKVpT3XH3Sw== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 30 Dec 2017 02:00:11 +0900 Message-Id: <1514566812-16781-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514566812-16781-1-git-send-email-yamada.masahiro@socionext.com> References: <1514566812-16781-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 7/8] mmc: sdhci-cadence: add HS200 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add HS200 timing setting and the MMC tuning callback. Signed-off-by: Masahiro Yamada --- drivers/mmc/sdhci-cadence.c | 87 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 78 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 921095b..8658126 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -52,6 +52,13 @@ #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d +/* + * The tuned val register is 6 bit-wide, but not the whole of the range is + * available. The range 0-42 seems to be available (then 43 wraps around to 0) + * but I am not quite sure if it is official. Use only 0 to 39 for safety. + */ +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 + struct sdhci_cdns_plat { struct mmc_config cfg; struct mmc mmc; @@ -135,20 +142,18 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) * The mode should be decided by MMC_TIMING_* like Linux, but * U-Boot does not support timing. Use the clock frequency instead. */ - if (clock <= 26000000) + if (clock <= 26000000) { mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */ - else if (clock <= 52000000) { + } else if (clock <= 52000000) { if (mmc->ddr_mode) mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; else mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; } else { - /* - * REVISIT: - * The IP supports HS200/HS400, revisit once U-Boot support it - */ - printf("unsupported frequency %d\n", clock); - return; + if (mmc->ddr_mode) + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; + else + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; } tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); @@ -161,6 +166,68 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_control_reg = sdhci_cdns_set_control_reg, }; +static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, + unsigned int val) +{ + void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06; + u32 tmp; + + if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) + return -EINVAL; + + tmp = readl(reg); + tmp &= ~SDHCI_CDNS_HRS06_TUNE; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); + tmp |= SDHCI_CDNS_HRS06_TUNE_UP; + writel(tmp, reg); + + return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), + 1); +} + +static int sdhci_cdns_execute_tuning(struct udevice *dev, unsigned int opcode) +{ + struct sdhci_cdns_plat *plat = dev_get_platdata(dev); + struct mmc *mmc = &plat->mmc; + int cur_streak = 0; + int max_streak = 0; + int end_of_streak = 0; + int i; + + /* + * This handler only implements the eMMC tuning that is specific to + * this controller. The tuning for SD timing should be handled by the + * SDHCI core. + */ + if (!IS_MMC(mmc)) + return -ENOSYS; + + if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200)) + return -EINVAL; + + for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { + if (sdhci_cdns_set_tune_val(plat, i) || + mmc_send_tuning(mmc, opcode, NULL)) { /* bad */ + cur_streak = 0; + } else { /* good */ + cur_streak++; + if (cur_streak > max_streak) { + max_streak = cur_streak; + end_of_streak = i; + } + } + } + + if (!max_streak) { + dev_err(dev, "no tuning point found\n"); + return -EIO; + } + + return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2); +} + +static struct dm_mmc_ops sdhci_cdns_mmc_ops; + static int sdhci_cdns_bind(struct udevice *dev) { struct sdhci_cdns_plat *plat = dev_get_platdata(dev); @@ -189,6 +256,8 @@ static int sdhci_cdns_probe(struct udevice *dev) host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; host->ops = &sdhci_cdns_ops; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; + sdhci_cdns_mmc_ops = sdhci_ops; + sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning; ret = mmc_of_parse(dev, &plat->cfg); if (ret) @@ -223,5 +292,5 @@ U_BOOT_DRIVER(sdhci_cdns) = { .probe = sdhci_cdns_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat), - .ops = &sdhci_ops, + .ops = &sdhci_cdns_mmc_ops, };