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[81.169.180.215]) by mx.google.com with ESMTP id d92si2789057edc.231.2018.03.26.07.29.22; Mon, 26 Mar 2018 07:29:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fAAhlu3c; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id DEE0AC21F1B; Mon, 26 Mar 2018 14:28:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 248D3C21F6D; Mon, 26 Mar 2018 14:27:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4A32EC21F1D; Mon, 26 Mar 2018 14:27:43 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id C66ECC21F1D for ; Mon, 26 Mar 2018 14:27:39 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id p9so3327770wmc.3 for ; Mon, 26 Mar 2018 07:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3F7e6WdTiSUuglgtHevNnLtl29Sx12NK4gYUNbq9peI=; b=fAAhlu3cVCZyrRQv4QAh6nEtytFxyZ7Ks81w1RIdL/GmYln57/IjUpN3XPvRG7clYf xv6S6/nJW26R4257qBLhpYNNUn2u9N9RgfvSVXUJWcyFY7l88UUxRAut7sbekdO0pgad LOrB8ebMu36CMShRscRgrzXJEtNxO8FZEmmuw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3F7e6WdTiSUuglgtHevNnLtl29Sx12NK4gYUNbq9peI=; b=d7wzrZPelDMppBSpCrsn6ymAQuoPWyLFB6497u+auDc/JCUauCwi5r4y7Qx0VjkLSI qHlqI3ditm6i+LIUNDz2cAmVrhozuF/Fn/7s5kb/2w8UtX0U04LHaAnFJ46Dq97jGTVH mW9jSsCq2C67GEAxQ4CboX4/HJEbjaHb0t5vBwrAxb1jvy0iF6b7IYn4lXz+NbIk9rDb Vbfu9E8szgna1y3I0yYkapDll/+COWRr97hYDQbTy7hf2/VBY4kG/Ov4DtVSx1s5W+y3 kazWdpMpVkQATrNP5CAACT8ZFYqLOAxfCG6RGMC23y0MZZSdgbksHSOxPBPpwKiDWPlz FG7A== X-Gm-Message-State: AElRT7GYeM7NGyiNZ6H5wz0u2M89TGsMZyCK+YSzMmg0umM9/Axyd24W ZdcYpx1hMOgQtq2Dto2m2sOPgR2h92U= X-Received: by 10.80.187.75 with SMTP id y69mr41128585ede.251.1522074458927; Mon, 26 Mar 2018 07:27:38 -0700 (PDT) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id a88sm10338634edf.64.2018.03.26.07.27.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Mar 2018 07:27:38 -0700 (PDT) From: Bryan O'Donoghue To: u-boot@lists.denx.de, fabio.estevam@nxp.com Date: Mon, 26 Mar 2018 15:27:33 +0100 Message-Id: <1522074454-16643-3-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522074454-16643-1-git-send-email-bryan.odonoghue@linaro.org> References: <1522074454-16643-1-git-send-email-bryan.odonoghue@linaro.org> Cc: rui.silva@linaro.org Subject: [U-Boot] [PATCH v3 2/3] imx: mx7: Add comment to describe OTP TESTER registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The tester registers provide a unique chip-level identifier which get_board_serial() returns in a "struct tag_serialnr". This patch documents the properties of the registers; in summary. 31:0 OCOTP_TESTER0 (most significant) - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID OCOTP_TESTER1 (least significant) 31:24 - The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 23:16 - The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 15:11 - The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID 10:0 - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID The 64 bits of data generate a unique serial number per-chip. Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx7/soc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 1602585..fb92a26 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -202,6 +202,27 @@ int arch_misc_init(void) #endif #ifdef CONFIG_SERIAL_TAG +/* + * OCOTP_TESTER + * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 + * OCOTP_TESTER describes a unique ID based on silicon wafer + * and die X/Y position + * + * OCOTOP_TESTER offset 0x410 + * 31:0 fuse 0 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID + * + * OCOTP_TESTER1 offset 0x420 + * 31:24 fuse 1 + * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID + * 23:16 fuse 1 + * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID + * 15:11 fuse 1 + * The wafer number of the wafer on which the device was fabricated/SJC + * CHALLENGE/ Unique ID + * 10:0 fuse 1 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID + */ void get_board_serial(struct tag_serialnr *serialnr) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;