From patchwork Thu Apr 23 13:25:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Madalin Bucur \(OSS\)" X-Patchwork-Id: 238381 List-Id: U-Boot discussion From: madalin.bucur at oss.nxp.com (Madalin Bucur) Date: Thu, 23 Apr 2020 16:25:13 +0300 Subject: [PATCH 03/12] ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB In-Reply-To: <1587648322-24795-1-git-send-email-madalin.bucur@oss.nxp.com> References: <1587648322-24795-1-git-send-email-madalin.bucur@oss.nxp.com> Message-ID: <1587648322-24795-4-git-send-email-madalin.bucur@oss.nxp.com> Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur --- arch/arm/dts/fsl-ls1043a-rdb.dts | 81 ++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/fsl-ls1043a.dtsi | 2 +- 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index 721b158..6e4ea5b 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright (C) 2015, Freescale Semiconductor + * Copyright 2020 NXP * * Mingkai Hu */ @@ -98,3 +99,83 @@ &duart1 { status = "okay"; }; + +#include "fsl-ls1043-post.dtsi" + +&fman0 { + ethernet at e0000 { + phy-handle = <&qsgmii_phy1>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet at e2000 { + phy-handle = <&qsgmii_phy2>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet at e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-txid"; + status = "okay"; + }; + + ethernet at e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-txid"; + status = "okay"; + }; + + ethernet at e8000 { + phy-handle = <&qsgmii_phy3>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet at ea000 { + phy-handle = <&qsgmii_phy4>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet at f0000 { /* 10GEC1 */ + phy-handle = <&aqr105_phy>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + mdio at fc000 { + rgmii_phy1: ethernet-phy at 1 { + reg = <0x1>; + }; + + rgmii_phy2: ethernet-phy at 2 { + reg = <0x2>; + }; + + qsgmii_phy1: ethernet-phy at 4 { + reg = <0x4>; + }; + + qsgmii_phy2: ethernet-phy at 5 { + reg = <0x5>; + }; + + qsgmii_phy3: ethernet-phy at 6 { + reg = <0x6>; + }; + + qsgmii_phy4: ethernet-phy at 7 { + reg = <0x7>; + }; + }; + + mdio at fd000 { + aqr105_phy: ethernet-phy at 1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 132 4>; + reg = <0x1>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index b159c3c..0a959f0 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -31,7 +31,7 @@ interrupts = <1 9 0xf08>; }; - soc { + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>;