From patchwork Thu Sep 27 19:03:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 147732 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp2386742lji; Thu, 27 Sep 2018 12:05:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV62einmM8ooYHQjkewkHgAxiX3b/5MzFj3tsNsq9yCxve3n6RYnNCEYARfH727gTvNQ4vnI6 X-Received: by 2002:a17:906:c19:: with SMTP id s25-v6mr3414432ejf.140.1538075114592; Thu, 27 Sep 2018 12:05:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538075114; cv=none; d=google.com; s=arc-20160816; b=V4PFstr7Qz4bTkHEMgJMTjHwVyElKrAMj5+fKNcxpelOX2EyWdU2CjWEjA9CtzwnD9 K81EgjKcmHqUOT676iHD/qEYJpwc7AtbYLNfp9gKJjfp0ARb1CiPjoxzO7X+mO+Qo/R+ rlHQjyvos+ZUAaySqnJ2Jfk4IdefHRsMmPb0qrizSQpLBBlGSDahw2/C81IYxyzBBx0P y4Kni3DYCGd2WR8TrjhdCM/mTiiBT406l9HJ3iIgfNoxPzO7KolKnVuuvR280oIrm6CZ OuGhWz8PNOUtCH3SPh4wXIp4HBIa2UlERpwwqFcjWnnfCv6nb26v512aN8s3bd+7Rkxg HFmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=pITW8IEvCYALVGUl8/g+1F7IItP2Fk9GRJbByo4hP9A=; b=GVNyNJOSW0PnwAbU4uRsQnfvsO1Jv479VDCgwdqLynlis9/DDgwiadq+MBVVslPFkw SmnJLI2AA7FxnwJcLeYU6dM5rhDWPpUNU6HpsT9+swdk1mpbOmgjPPAfeDymMApCNPd+ D1EcgrAnLCi8I8KEIOu/+CRlimSsl4dFCRzjoO9KWPEGb0BMsWo8l7ke2MCVWip2p2fn 4F+Vqtgjz9SSs0Spo3HrcL7gc6VLj5BLH8bx7WlD5z2Pox6aPuWT87V6CKKKFUSgASwK O+Bn/AjU9OuhljTmaeJHrLtPxsSt7/J7cnMB6qex6+3guHY8MBc3gs70QiXDvZis7T1q hfAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="aA/BkNdw"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b16-v6si1124247edh.182.2018.09.27.12.05.14; Thu, 27 Sep 2018 12:05:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="aA/BkNdw"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 047EDC21DD7; Thu, 27 Sep 2018 19:04:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6B1F0C21DFF; Thu, 27 Sep 2018 19:04:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D45D0C21DF8; Thu, 27 Sep 2018 19:03:40 +0000 (UTC) Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by lists.denx.de (Postfix) with ESMTPS id B1B90C21DA1 for ; Thu, 27 Sep 2018 19:03:39 +0000 (UTC) Received: by mail-pf1-f193.google.com with SMTP id m77-v6so2545545pfi.8 for ; Thu, 27 Sep 2018 12:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Uj7UGXpVKEvMLcl/BldGd4WKXsDmIIHgDlw0AojHITU=; b=aA/BkNdw4c14RRt4md9w2k9SmU3pnW0PTDwbydQCC6iyutKSiqlqpz/dU8rGwcjP9F /FscZSjlCbAHHyrTBOz6YDeGMfrryrfwRc8udCgp0tb1LsnnYlz+ijtx8PAUAv737Mai DvZxpiS3iw4fifRzFfA4bvK4AjcqykMqAA2vE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Uj7UGXpVKEvMLcl/BldGd4WKXsDmIIHgDlw0AojHITU=; b=TW2kZ6LtvDxX9WYOF0QYlmQF51ZRGWRibPev2QUTQVfqRiGS70DICREMEtZXs6uM+I cffK/FMIAM0YKChhpIVhHb7pYEJaGVHKqExLAubzijiyw4FhdxisKNvpy9pLwCxRPWt7 H+iIWQT17EdAgDHcZmJ3irirPOWDPnjNuV9ImdbtrcHNP0ovTncq0VqEIW7rtEAso/Cr J6exe+BZJmOVnnZ5DxolPRkyRXKj0AR2pBV87Xp+ukM6stjvFV192yvSJlgxQPDxh1Cw mn+UhNYnEFH7e5mYhymWnQt8p5P4nx0b70szoqytHoMvS4Yfjf8DScup9MUi73ef9T/h KtMA== X-Gm-Message-State: ABuFfojfE+yqmo0XepcXy3gQmY0HFE+QQ/BxF7euLLe9mXqV/YuV8IzL SX9dj2CNGxiIrpt15VwYk6XS X-Received: by 2002:a17:902:9a82:: with SMTP id w2-v6mr12596696plp.109.1538075017849; Thu, 27 Sep 2018 12:03:37 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:620c:e606:55b5:4f81:aee3:95c7]) by smtp.gmail.com with ESMTPSA id v8-v6sm4408895pff.120.2018.09.27.12.03.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Sep 2018 12:03:37 -0700 (PDT) From: Manivannan Sadhasivam To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Fri, 28 Sep 2018 00:33:00 +0530 Message-Id: <20180927190301.9642-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927190301.9642-1-manivannan.sadhasivam@linaro.org> References: <20180927190301.9642-1-manivannan.sadhasivam@linaro.org> Cc: tom@vamrs.com, daniel.lezcano@linaro.org, amit.kucheria@linaro.org, dev@vamrs.com, u-boot@lists.denx.de, Manivannan Sadhasivam , stephen@vamrs.com Subject: [U-Boot] [PATCH v3 3/4] rockchip: rk3399: Add Rock960 CE board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add board support for Rock960 CE board from Vamrs. This board utilizes common Rock960 family support. Following peripherals are tested and known to work: * USB 2.0 * MMC This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which is being used on the board. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Simon Glass Tested-by: Peter Robinson Reviewed-by: Philipp Tomsich --- Changes in v3: * Add config options for USB to Ethernet and USB2 PHY Changes in v2: * Added missing config options for USB/uSD * Fixed the commit description for DDR speed arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock960.dts | 45 + .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +++++++++++++++++ configs/rock960-rk3399_defconfig | 69 + 4 files changed, 1651 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock960.dts create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi create mode 100644 configs/rock960-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa2272627..9b891826b73 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rock960.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts new file mode 100644 index 00000000000..25c58b42611 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" +#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi new file mode 100644 index 00000000000..d14e833d228 --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi @@ -0,0 +1,1536 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2018 Manivannan Sadhasivam + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 0x1 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 800 + 6 + 2 + 9 + 1 + 0x00000700 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x01001f40 + 0x00000000 + 0x00000101 + 0x00020100 + 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CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y