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[81.169.180.215]) by mx.google.com with ESMTP id g3-v6si4195203edh.109.2018.10.31.14.23.30; Wed, 31 Oct 2018 14:23:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 895CAC220DC; Wed, 31 Oct 2018 21:23:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4701CC221C6; Wed, 31 Oct 2018 21:21:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F24F2C22045; Wed, 31 Oct 2018 21:21:53 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id B733AC21FED for ; Wed, 31 Oct 2018 21:21:52 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLmXt072326; Wed, 31 Oct 2018 16:21:48 -0500 Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLmbp068349 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:48 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:48 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLltH000319; Wed, 31 Oct 2018 16:21:48 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLlx26207; Wed, 31 Oct 2018 16:21:47 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:44 -0500 Message-ID: <20181031212145.32761-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 6/7] driver: net: ti: cpsw: switch to use common mdio lib X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update TI CPSW driver to re-use common mdio lib Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- drivers/net/ti/cpsw.c | 134 +++----------------------------------------------- 1 file changed, 6 insertions(+), 128 deletions(-) diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index fe43d14..f5fd02e 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -21,11 +21,11 @@ #include #include +#include "cpsw_mdio.h" + DECLARE_GLOBAL_DATA_PTR; #define BITMASK(bits) (BIT(bits) - 1) -#define PHY_REG_MASK 0x1f -#define PHY_ID_MASK 0x1f #define NUM_DESCS (PKTBUFSRX * 2) #define PKT_MIN 60 #define PKT_MAX (1500 + 14 + 4 + 4) @@ -76,37 +76,8 @@ DECLARE_GLOBAL_DATA_PTR; * unexpected controller lock ups. Ideally, we should never ever hit this * scenario in practice. */ -#define MDIO_TIMEOUT 100 /* msecs */ #define CPDMA_TIMEOUT 100 /* msecs */ -struct cpsw_mdio_regs { - u32 version; - u32 control; -#define CONTROL_IDLE BIT(31) -#define CONTROL_ENABLE BIT(30) - - u32 alive; - u32 link; - u32 linkintraw; - u32 linkintmasked; - u32 __reserved_0[2]; - u32 userintraw; - u32 userintmasked; - u32 userintmaskset; - u32 userintmaskclr; - u32 __reserved_1[20]; - - struct { - u32 access; - u32 physel; -#define USERACCESS_GO BIT(31) -#define USERACCESS_WRITE BIT(30) -#define USERACCESS_ACK BIT(29) -#define USERACCESS_READ (0) -#define USERACCESS_DATA (0xffff) - } user[0]; -}; - struct cpsw_regs { u32 id_ver; u32 control; @@ -484,100 +455,6 @@ static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, __raw_writel(tmp, priv->ale_regs + offset); } -static struct cpsw_mdio_regs *mdio_regs; - -/* wait until hardware is ready for another user access */ -static inline u32 wait_for_user_access(void) -{ - u32 reg = 0; - int timeout = MDIO_TIMEOUT; - - while (timeout-- && - ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) - udelay(10); - - if (timeout == -1) { - printf("wait_for_user_access Timeout\n"); - return -ETIMEDOUT; - } - return reg; -} - -/* wait until hardware state machine is idle */ -static inline void wait_for_idle(void) -{ - int timeout = MDIO_TIMEOUT; - - while (timeout-- && - ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) - udelay(10); - - if (timeout == -1) - printf("wait_for_idle Timeout\n"); -} - -static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, - int dev_addr, int phy_reg) -{ - int data; - u32 reg; - - if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) - return -EINVAL; - - wait_for_user_access(); - reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | - (phy_id << 16)); - __raw_writel(reg, &mdio_regs->user[0].access); - reg = wait_for_user_access(); - - data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; - return data; -} - -static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, - int phy_reg, u16 data) -{ - u32 reg; - - if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) - return -EINVAL; - - wait_for_user_access(); - reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | - (phy_id << 16) | (data & USERACCESS_DATA)); - __raw_writel(reg, &mdio_regs->user[0].access); - wait_for_user_access(); - - return 0; -} - -static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) -{ - struct mii_dev *bus = mdio_alloc(); - - mdio_regs = (struct cpsw_mdio_regs *)mdio_base; - - /* set enable and clock divider */ - __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); - - /* - * wait for scan logic to settle: - * the scan time consists of (a) a large fixed component, and (b) a - * small component that varies with the mii bus frequency. These - * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x - * silicon. Since the effect of (b) was found to be largely - * negligible, we keep things simple here. - */ - udelay(1000); - - bus->read = cpsw_mdio_read; - bus->write = cpsw_mdio_write; - strcpy(bus->name, name); - - mdio_register(bus); -} - /* Set a self-clearing bit in a register, and wait for it to clear */ static inline void setbit_and_wait_for_clear32(void *addr) { @@ -1003,7 +880,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) static void cpsw_phy_addr_update(struct cpsw_priv *priv) { struct cpsw_platform_data *data = &priv->data; - u16 alive = mdio_regs->alive & GENMASK(15, 0); + u16 alive = cpsw_mdio_get_alive(priv->bus); int active = data->active_slave; int new_addr = ffs(alive) - 1; @@ -1044,11 +921,12 @@ int _cpsw_register(struct cpsw_priv *priv) idx = idx + 1; } - cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); + priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0); + if (!priv->bus) + return -EFAULT; cpsw_phy_addr_update(priv); - priv->bus = miiphy_get_dev_by_name(priv->dev->name); for_active_slave(slave, priv) cpsw_phy_init(priv, slave);