From patchwork Wed Nov 14 09:01:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 151051 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5438132ljp; Wed, 14 Nov 2018 01:04:10 -0800 (PST) X-Google-Smtp-Source: AJdET5cqemJ+DgdjFC4Mrp55USIvsxS1UkdRzgIIggOyXaxK2aWS+fQwTV4VvWvHpZpyIkl4elQp X-Received: by 2002:a50:8907:: with SMTP id e7mr1372120ede.252.1542186250231; Wed, 14 Nov 2018 01:04:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542186250; cv=none; d=google.com; s=arc-20160816; b=L4dGOhvsWnm1VUn+NU7v+7qZQekM9m7m2D4wJqKANljlpfl4pb2YHcEFukUhOEJP/N IDhVRJD6Yr18d2iNHkx/UC8kunR7agga+aMPcbek0GZ8qYNxkeEYgAVBt5Lhrj6NI1fM Dzz96J+pdI9fk7FNHsia2J5PTUTfj8MKibrZ71ABU15+YD0LvE0czmde1Bt68X7sKzvf 5L8ql0cZ7rsHFMpoFQa4Nze/R7yzASInja7qKAvnASRQ1hDV0PcfDvY9UmpMaDjiuVaN 7yWRjtesH8IwmvNz1ePp8ayfmyo+WlCkQj8i1ctlZ9sVCMCrNMlWxzSozcMr5kp5yc8E 1Efg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=DGnFd3DTS5dUofryqUAeXJDYp//9tcNMnBXMmjdZ2pE=; b=0ttP8GoCcXy1hxf096608yBhyJSGpNohvUU9AAjdI47zdRMQbZRC4uYm4Yd8j7Y4TS Xw3WTYdBg/DiooT+LUBCAq43NppUh35AbfddYBZyobbm+hNV08L2//kasqT/cloZrSlH 0EwauuUaHyAMLY1JUtm13nZdvVlzSzXNpcanOW+QS6wxL5lZwICxuP9hCm4gzuh3iuQB ooN7MPAjKPIWcSb0wT1AB7NedKSlIGeaVsQdJf3Lzx94x+Ecqjd/WDiMwc9bEEysYQ6z bfZcJ2SfzUZcy2uFgWsNY5lWdOwK3mCcyhAGONJdtWsd/+bdFTwlqRUht0d55hsfkNkB iW4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EMDkDec0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id i88-v6si778978edd.399.2018.11.14.01.04.09; Wed, 14 Nov 2018 01:04:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EMDkDec0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id A3A7CC2206D; Wed, 14 Nov 2018 09:03:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8EEC8C224C4; Wed, 14 Nov 2018 09:01:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E5482C2205D; Wed, 14 Nov 2018 09:01:41 +0000 (UTC) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by lists.denx.de (Postfix) with ESMTPS id 1ACB9C224AA for ; Wed, 14 Nov 2018 09:01:38 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id i73-v6so9316804wmd.5 for ; Wed, 14 Nov 2018 01:01:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LvD5klWzDZi5nk7m6fiOYmn5U+0L2TkxOuVMffXfW2A=; b=EMDkDec02d28iVexeHdvQu9RYRCXXzZMvdvimyaWKySiwwI2VgaXc4B9tS9gofy+ql g8ZLsQsfXXz6zTDSCLbp5x9AZCdTZ2rU23OY5snZNpSAAnrbb9pALmWBbfAt7hQdAF4C VFh66+nSe3RWn9VNtmoF3BsNNM0yhqzM9z3LM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LvD5klWzDZi5nk7m6fiOYmn5U+0L2TkxOuVMffXfW2A=; b=q+IPkWb2xBKwlLnj5vPA6FMoCYoCbTCDE9EnuGOT+BBZRLDAuVpz/EKPrKrqkGTiCe jJilFxSnoth02odoHMzr8uh6eqtd8QdpOo4h4UgHRpG6+vVkM1WrV7rUwNiWtxf+JrO/ 6Sz7uSMss6Ymd1jQI1h5DndaWrz8MXg5Dz1dvogi1iKb7VDhZ82L97ORaGcmN4Tc9FTd B1JPNXnxoC6ofWeXwvu0CCxY/9STp794BxxxqvTv8sKMW900kUrsedLxAkao+PruuxbV GT0qHO6QjBgLCiJMG706Cqtpu1qbwvjG2lOm5HDd0neACT8D2dM/JsWzvOWU/jyN5MaZ PxTw== X-Gm-Message-State: AGRZ1gK49oqinklkWAOMixTfxoOZie7GYOcMU9ZB746vctjOGuWQYFSS zKjzWkhthDZeFsKPWgi/gq78kQ== X-Received: by 2002:a1c:ce8d:: with SMTP id e135-v6mr1041424wmg.3.1542186097707; Wed, 14 Nov 2018 01:01:37 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id j125-v6sm14474871wmb.12.2018.11.14.01.01.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:01:37 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Wed, 14 Nov 2018 10:01:14 +0100 Message-Id: <20181114090114.7727-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090114.7727-1-benjamin.gaignard@st.com> References: <20181114090114.7727-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 4/4] pinctrl: stm32: make pinctrl use hwspinlock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 2: - be more verbose in commit message - log the error after hwspinlock_get_by_index() arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ drivers/pinctrl/pinctrl_stm32.c | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fc277dd7d2..7a9b742d36 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -369,6 +369,10 @@ status = "okay"; }; +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 31285cdd57..5b63a2de15 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -19,12 +20,20 @@ static int stm32_gpio_config(struct gpio_desc *desc, { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct hwspinlock *hws = dev_get_priv(desc->dev->parent); u32 index; + int ret; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ret = hwspinlock_lock_timeout(hws, 1); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -39,6 +48,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(hws); + return 0; } @@ -176,6 +187,20 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, } #endif /* PINCTRL_FULL */ +static int stm32_pinctrl_probe(struct udevice *dev) +{ + struct hwspinlock *hws = dev_get_priv(dev); + int err; + + /* hwspinlock property is optional, just log the error */ + err = hwspinlock_get_by_index(dev, 0, hws); + if (err) + debug("%s: hwspinlock_get_by_index may have failed (%d)\n", + __func__, err); + + return 0; +} + static struct pinctrl_ops stm32_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCTRL_FULL) .set_state = stm32_pinctrl_set_state, @@ -200,4 +225,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, .bind = dm_scan_fdt_dev, + .probe = stm32_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct hwspinlock), };