From patchwork Wed Feb 19 13:04:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 236585 List-Id: U-Boot discussion From: igor.opaniuk at gmail.com (Igor Opaniuk) Date: Wed, 19 Feb 2020 15:04:49 +0200 Subject: [PATCH v1 1/4] ARM: dts: imx8qm-apalis: replace dm-spl with dm-pre-proper Message-ID: <20200219130452.8895-1-igor.opaniuk@gmail.com> From: Igor Opaniuk For non-SPL/TPL setups dm-spl, dm-tpl, dm-pre-proper, dm-pre-reloc are handled equally, forcing the nodes with these properties to be accessible and device being probed before pre-relocation of U-Boot proper (drivers/core/util.c): bool ofnode_pre_reloc(ofnode node) { /* for SPL and TPL the remaining nodes after the fdtgrep 1st pass * had property dm-pre-reloc or u-boot,dm-spl/tpl. * They are removed in final dtb (fdtgrep 2nd pass) */ return true; if (ofnode_read_bool(node, "u-boot,dm-pre-reloc")) return true; if (ofnode_read_bool(node, "u-boot,dm-pre-proper")) return true; /* * In regular builds individual spl and tpl handling both * count as handled pre-relocation for later second init. */ if (ofnode_read_bool(node, "u-boot,dm-spl") || ofnode_read_bool(node, "u-boot,dm-tpl")) return true; return false; } Howewer, to avoid confusion in future, replace dm-spl `%s/dm-spl/dm-pre-proper/g` properties to dm-pre-proper to explicitly state that they are handled during pre-relocation stage of U-Boot proper. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 62 +++++++++++----------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index 7b1a9550e4..6cdf58c8ad 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -4,125 +4,125 @@ */ &mu { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &clk { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &iomuxc { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio4 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio5 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio6 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_lsio_gpio7 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &pd_conn_sdch2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio4 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio5 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio6 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &gpio7 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart0 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &lpuart3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc1 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc2 { - u-boot,dm-spl; + u-boot,dm-pre-proper; }; &usdhc3 { - u-boot,dm-spl; + u-boot,dm-pre-proper; };