From patchwork Fri Feb 21 01:25:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 236662 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Fri, 21 Feb 2020 09:25:06 +0800 Subject: [PATCH 2/2] configs: socfpga: Add QSPI boot for Arria 10 SoCDK In-Reply-To: <20200221012506.5042-1-ley.foon.tan@intel.com> References: <20200221012506.5042-1-ley.foon.tan@intel.com> Message-ID: <20200221012506.5042-2-ley.foon.tan@intel.com> Add QSPI boot settings for Arria 10 SoCDK. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_arria10_socdk.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 645e66e6b0..e1d01c095f 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -39,6 +39,15 @@ /* SPL memory allocation configuration, this is for FAT implementation */ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 +#define KERNEL_FIT_ADDR __stringify(0x1200000) + +#define SOCFPGA_BOOT_SETTINGS \ + "kernelfit_addr=" KERNEL_FIT_ADDR "\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + "root=/dev/mtdblock1 rw rootfstype=jffs2;" \ + "bootm ${scriptaddr}\0" \ + "qspiload=sf probe; sf read ${scriptaddr} ${kernelfit_addr}\0" \ + /* The rest of the configuration is shared */ #include