From patchwork Fri Feb 28 21:05:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 237021 List-Id: U-Boot discussion From: seanga2 at gmail.com (Sean Anderson) Date: Fri, 28 Feb 2020 16:05:51 -0500 Subject: [PATCH v5 33/33] riscv: Add Sipeed Maix support In-Reply-To: <20200228210552.615672-1-seanga2@gmail.com> References: <20200228210552.615672-1-seanga2@gmail.com> Message-ID: <20200228210552.615672-34-seanga2@gmail.com> The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at . Documentation for the Kendryte K210 is located at . However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at . Signed-off-by: Sean Anderson --- Changes in v5: - Configure relocation location with CONFIG_SYS_SDRAM_* - Enable ram clocks - Add pinmux/gpio/led support - Remove (broken) MMC support - Store the environment in flash - Add partitions - Add bootcmd - Add docs for pinctrl and booting Changes in v4: - Rework documentation to be organized by board mfg not cpu mfg - Update docs to reflect working SPI support - Add proper spi support - Don't define unneecessary macros in config.h - Lower the default stack so it isn't clobbered on relocation - Update MAINTAINERS - Update copyright Changes in v3: - Reorder to be last in the patch series - Add documentation for the board - Generate defconfig with "make savedefconfig" - Update Kconfig to imply most features we need - Update MAINTAINERS Changes in v2: - Select CONFIG_SYS_RISCV_NOCOUNTER - Imply CONFIG_CLK_K210 - Remove spurious references to CONFIG_ARCH_K210 - Remove many configs from defconfig where the defaults were fine - Add a few "not set" lines to suppress unneeded defaults - Reduce pre-reloc malloc space, now that clocks initialization happens later arch/riscv/Kconfig | 4 + board/sipeed/maix/Kconfig | 72 ++++++++++ board/sipeed/maix/MAINTAINERS | 11 ++ board/sipeed/maix/Makefile | 5 + board/sipeed/maix/maix.c | 54 +++++++ configs/sipeed_maix_bitm_defconfig | 16 +++ doc/board/index.rst | 1 + doc/board/sipeed/index.rst | 9 ++ doc/board/sipeed/maix.rst | 223 +++++++++++++++++++++++++++++ include/configs/sipeed-maix.h | 24 ++++ 10 files changed, 419 insertions(+) create mode 100644 board/sipeed/maix/Kconfig create mode 100644 board/sipeed/maix/MAINTAINERS create mode 100644 board/sipeed/maix/Makefile create mode 100644 board/sipeed/maix/maix.c create mode 100644 configs/sipeed_maix_bitm_defconfig create mode 100644 doc/board/sipeed/index.rst create mode 100644 doc/board/sipeed/maix.rst create mode 100644 include/configs/sipeed-maix.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b7a5757584..d016dd75d7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT config TARGET_SIFIVE_FU540 bool "Support SiFive FU540 Board" +config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" + endchoice config SYS_ICACHE_OFF @@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" +source "board/sipeed/maix/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig new file mode 100644 index 0000000000..939eb4829a --- /dev/null +++ b/board/sipeed/maix/Kconfig @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2019-20 Sean Anderson + +if TARGET_SIPEED_MAIX + +config SYS_BOARD + default "maix" + +config SYS_VENDOR + default "sipeed" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "sipeed-maix" + +config SYS_TEXT_BASE + default 0x80000000 + +config DEFAULT_DEVICE_TREE + default "k210-maix-bit" + +config NR_CPUS + default 2 + +config NR_DRAM_BANKS + default 3 + +config SF_DEFAULT_BUS + default 3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select GENERIC_RISCV + select RISCV_PRIV_1_9 + imply SMP + imply OF_BOARD_SETUP + imply DM_SERIAL + imply SIFIVE_SERIAL + imply SIFIVE_CLINT + imply POWER_DOMAIN + imply SIMPLE_PM_BUS + imply CLK_CCF + imply CLK_COMPOSITE_CCF + imply CLK_K210 + imply DM_RESET + imply RESET_SYSCON + imply SYSRESET + imply SYSRESET_SYSCON + imply PINCTRL + imply PINCONF + imply PINCTRL_K210 + imply DM_GPIO + imply DWAPB_GPIO + imply SIFIVE_GPIO + imply CMD_GPIO + imply LED + imply LED_GPIO + imply SPI + imply DESIGNWARE_SPI + imply SPI_FLASH_WINBOND + imply DM_MTD + imply SPI_FLASH_MTD + imply CMD_MTD + imply ENV_IS_IN_SPI_FLASH + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply WDT + imply DESIGNWARE_WATCHDOG +endif diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS new file mode 100644 index 0000000000..1f33882e1e --- /dev/null +++ b/board/sipeed/maix/MAINTAINERS @@ -0,0 +1,11 @@ +Sipeed Maix BOARD +M: Sean Anderson +S: Maintained +F: arch/riscv/dts/k210.dtsi +F: arch/riscv/dts/k210-maix-bit.dts +F: board/sipeed/maix/ +F: configs/sipeed_maix_defconfig +F: doc/board/sipeed/ +F: include/configs/sipeed-maix.h +F: include/dt-bindings/*/k210-sysctl.h +F: test/dm/k210_pll.c diff --git a/board/sipeed/maix/Makefile b/board/sipeed/maix/Makefile new file mode 100644 index 0000000000..4acff5b31e --- /dev/null +++ b/board/sipeed/maix/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2019 Western Digital Corporation or its affiliates. + +obj-y += maix.o diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c new file mode 100644 index 0000000000..c126cb5d67 --- /dev/null +++ b/board/sipeed/maix/maix.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Sean Anderson + */ + +#include +#include +#include +#include + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_SDRAM_SIZE; +} + +int board_init(void) +{ + int ret; + ofnode bank = ofnode_null(); + + /* Enable RAM clocks */ + while (true) { + struct clk clk; + + bank = ofnode_by_prop_value(bank, "device_type", "memory", + sizeof("memory")); + if (ofnode_equal(bank, ofnode_null())) + break; + + ret = clk_get_by_index_nodev(bank, 0, &clk); + if (ret) + continue; + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) + return ret; + } + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + int i; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = bd->bi_dram[i].start; + size[i] = bd->bi_dram[i].size; + } + + return fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); +} diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig new file mode 100644 index 0000000000..7f644e7a37 --- /dev/null +++ b/configs/sipeed_maix_bitm_defconfig @@ -0,0 +1,16 @@ +CONFIG_RISCV=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x7C000 +CONFIG_ENV_OFFSET_REDUND=0x7E000 +CONFIG_TARGET_SIPEED_MAIX=y +CONFIG_ARCH_RV64I=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe;mtd read kernel 80000000;go 80000000" +CONFIG_MTDIDS_DEFAULT="nor0=spi3.0" +CONFIG_MTDPARTS_DEFAULT="spi3.0:496k(u-boot),16k(env),5632k(kernel),10240k(data)" +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +# CONFIG_NET is not set +# CONFIG_INPUT is not set +# CONFIG_DM_ETH is not set +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/index.rst b/doc/board/index.rst index b8b956d730..54cbc5c874 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -16,4 +16,5 @@ Board-specific doc renesas/index rockchip/index sifive/index + sipeed/index xilinx/index diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst new file mode 100644 index 0000000000..92da47fddd --- /dev/null +++ b/doc/board/sipeed/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Kendryte +======== + +.. toctree:: + :maxdepth: 2 + + maix diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst new file mode 100644 index 0000000000..c5c2e24ea5 --- /dev/null +++ b/doc/board/sipeed/maix.rst @@ -0,0 +1,223 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2020 Sean Anderson + +Maix Bit +======== + +Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor, +a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate +neural network processing and other "ai" tasks. This includes a "KPU" neural +network processor, an audio processor supporting beamforming reception, and a +digital video port supporting capture and output at VGA resolution. Other +peripherals include 8M of SRAM (accessible with and without caching); remappable +pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; +and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; +on-board usb-serial bridges; ports for cameras, displays, and sd cards; and +ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but +the boards are fairly similar. + +Documentation for Maix boards is available from +`Sipeed's website `_. +Documentation for the Kendryte K210 is available from +`Kendryte's website `_. However, hardware +details are rather lacking, so most technical reference has been taken from the +`standalone sdk `_. + +Build and boot steps +-------------------- + +To build u-boot, run + +.. code-block:: none + + make sipeed_maix_bitm_defconfig + make CROSS_COMPILE= + +To flash u-boot to a maix bit, run + +.. code-block:: none + + kflash -tp /dev/ -B bit_mic u-boot-dtb.bin + +Boot output should look like the following: + +.. code-block:: none + + + U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) + + DRAM: 8 MiB + WDT: Started with servicing (60s timeout) + MMC: spi at 53000000:slot at 0: 0 + In: serial at 38000000 + Out: serial at 38000000 + Err: serial at 38000000 + Hit any key to stop autoboot: 0 + SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB + Reading 5242880 byte(s) at offset 0x00000000 + ## Starting application at 0x80000000 ... + +Flashing Images +--------------- + +To flash a kernel, transfer it over serial, then write it to the kernel +partition. + +.. code-block:: none + + => loady 80000000 1500000 + ## Switch baudrate to 1500000 bps and press ENTER ... + + *** baud: 1500000 + + *** baud: 1500000 *** + ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps... + C + *** file: loader.bin + $ sz -vv loader.bin + Sending: loader.bin + Bytes Sent:2478208 BPS:72937 + Sending: + Ymodem sectors/kbytes sent: 0/ 0k + Transfer complete + + *** exit status: 0 *** + ## Total Size = 0x0025d052 = 2478162 Bytes + ## Switch baudrate to 115200 bps and press ESC ... + + *** baud: 115200 + + *** baud: 115200 *** + => sf probe + SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB + => mtd write kernel 80000000 0 25d052 + Writing 2478162 byte(s) at offset 0x00000000 + +**NB:** kflash adds a 5-byte header to payloads (and a 32-byte trailer) to all +payloads it flashes. If you use kflash to flash your payload, you will need to +account for this header when specifying what offset in spi flash to load from. + +Partition Scheme +^^^^^^^^^^^^^^^^ + +There is no partition scheme specified by the manufacturer. The only requirement +imposed by the firmware is that offset 0 will be loaded and ran. The default +partition scheme is + +========= ======== ====== +Partition Offset Size +========= ======== ====== +u-boot 0x000000 496k +env 0x07C000 16k +kernel 0x080000 5M +data 0x580000 10.5M +========= ======== ====== + +Pin Assignment +-------------- + +The K210 contains a Fully Programmable I/O Array (FPIOA), which can remap any of +its 256 input functions to any any of 48 output pins. The following table has +the default pin assignments for the BitM. + +===== ========== ======= +Pin Function Comment +===== ========== ======= +IO_0 JTAG_TCLK +IO_1 JTAG_TDI +IO_2 JTAG_TMS +IO_3 JTAG_TDO +IO_4 UARTHS_RX +IO_5 UARTHS_TX +IO_6 GPIOHS_1 +IO_7 GPIOHS_2 +IO_8 GPIO_0 +IO_9 GPIO_1 +IO_10 GPIO_2 +IO_11 GPIO_3 +IO_12 GPIO_4 Green LED +IO_13 GPIO_5 Red LED +IO_14 GPIO_6 Blue LED +IO_15 GPIO_7 +IO_16 GPIOHS_0 ISP +IO_17 GPIOHS_3 +IO_18 I2S0_SCLK MIC CLK +IO_19 I2S0_WS MIC WS +IO_20 I2S0_IN_D0 MIC SD +IO_21 GPIOHS_4 +IO_22 GPIOHS_5 +IO_23 GPIOHS_6 +IO_24 GPIOHS_7 +IO_25 GPIOHS_8 +IO_26 SPI1_D1 MMC MISO +IO_27 SPI1_SCLK MMC CLK +IO_28 SPI1_D0 MMC MOSI +IO_29 GPIOHS_31 MMC CS +IO_30 GPIOHS_9 +IO_31 GPIOHS_10 +IO_32 GPIOHS_11 +IO_33 GPIOHS_12 +IO_34 GPIOHS_13 +IO_35 GPIOHS_14 +IO_36 GPIOHS_28 Panel CS +IO_37 GPIOHS_29 Panel RST +IO_38 GPIOHS_30 Panel DC +IO_39 SPI0_SCK Panel WR +IO_40 SCCP_SDA +IO_41 SCCP_SCLK +IO_42 DVP_RST +IO_43 DVP_VSYNC +IO_44 DVP_PWDN +IO_45 DVP_HSYNC +IO_46 DVP_XCLK +IO_47 DVP_PCLK +===== ========== ======= + +Over- and Under-clocking +------------------------ + +To change the clock speed of the K210, you will need to enable +``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a +section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following: + +.. code-block:: dts + + &sysclk { + assigned-clocks = <&sysclk K210_CLK_PLL0>; + assigned-clock-rates = <800000000>; + }; + +There are three PLLs on the K210: PLL0 is the parent of most of the components, +including the CPU and RAM. PLL1 is the parent of the neural network coprocessor. +PLL2 is the parent of the sound processing devices. Note that child clocks of +PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is +running at 800 MHz, then the CPU will run at 400 MHz. This is the example given +above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz. + +It is possible to set PLL2's parent to PLL0. The plls are more accurate when +converting between similar frequencies. This makes it easier to get an accurate +frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz. +On this device, the I2S serial clock runs at 64 times the sample rate. +Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If +PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's +default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This +results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If, +instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of +2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136 +yields a serial clock of about 2.8228 MHz. This results in a sample rate of +44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the +following example: + +.. code-block:: dts + + &sysclk { + assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>; + assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>; + assigned-clock-rates = <390000000>, <383846400>; + }; + +There are a couple of quirks to the PLLs. First, there are more frequency ratios +just above and below 1.0, but there is a small gap around 1.0. To be explicit, +if the input frequency is 100 MHz, it would be impossible to have an output of +99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO, +so higher input/output frequencies will be less accurate than lower ones. diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h new file mode 100644 index 0000000000..a46473fc78 --- /dev/null +++ b/include/configs/sipeed-maix.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson + */ + +#ifndef CONFIGS_SIPEED_MAIX_H +#define CONFIGS_SIPEED_MAIX_H + +#include + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* Start just below the second bank so we don't clobber it during reloc */ +#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* Don't relocate into AI ram since it isn't set up yet */ +#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M) + +/* For early init */ +#define K210_SYSCTL_BASE 0x50440000 + +#endif /* CONFIGS_SIPEED_MAIX_H */