From patchwork Wed Mar 4 04:39:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keerthy X-Patchwork-Id: 243194 List-Id: U-Boot discussion From: j-keerthy at ti.com (Keerthy) Date: Wed, 4 Mar 2020 10:09:59 +0530 Subject: [PATCH v2 1/3] arm: dts: k3-j721e: Enable ospi1/qspi In-Reply-To: <20200304044001.5346-1-j-keerthy@ti.com> References: <20200304044001.5346-1-j-keerthy@ti.com> Message-ID: <20200304044001.5346-2-j-keerthy@ti.com> Enable the ospi1/qspi for both r5 and a72 configurations. Signed-off-by: Keerthy --- Changes in v2: * Moved the pin definitions out of u-boot.dtsi to r5 and a72 based dts files. .../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 14 ++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index d422100d42..7b01e4204f 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -365,3 +365,15 @@ u-boot,dm-spl; }; }; + +&ospi1 { + u-boot,dm-spl; + + flash at 0 { + u-boot,dm-spl; + }; +}; + +&mcu_fss0_ospi1_pins_default { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index ebea9efa58..44da8eabc2 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -134,6 +134,20 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + u-boot,dm-spl; + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ + J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ + J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ + J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ + J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ + J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ + J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ + >; + }; }; &main_pmx0 {