From patchwork Thu Mar 5 18:53:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 243255 List-Id: U-Boot discussion From: seanga2 at gmail.com (Sean Anderson) Date: Thu, 5 Mar 2020 13:53:27 -0500 Subject: [PATCH v1 7/8] riscv: Add pinmux and gpio bindings for Kendryte K210 In-Reply-To: <20200305185328.951011-1-seanga2@gmail.com> References: <20200305185328.951011-1-seanga2@gmail.com> Message-ID: <20200305185328.951011-8-seanga2@gmail.com> This patch adds the necessary device tree bindings. Signed-off-by: Sean Anderson --- arch/riscv/dts/k210-maix-bit.dts | 196 +++++++++++++++++++++++++++++++ arch/riscv/dts/k210.dtsi | 43 ++++++- 2 files changed, 234 insertions(+), 5 deletions(-) diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts index 5b32c5fd5f..c0ec572552 100644 --- a/arch/riscv/dts/k210-maix-bit.dts +++ b/arch/riscv/dts/k210-maix-bit.dts @@ -17,6 +17,22 @@ stdout-path = "serial0:115200"; }; + gpio-leds { + compatible = "gpio-leds"; + + green { + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + red { + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + blue { + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -39,9 +55,189 @@ }; &uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&fpioa_gpio>; + pinctrl-names = "default"; status = "okay"; }; &i2s0 { #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&fpioa { + status = "okay"; + + fpioa_uarths: uarths { + rx { + function = "UARTHS_RX"; + pins = "IO_4"; + }; + tx { + function = "UARTHS_TX"; + pins = "IO_5"; + }; + }; + + fpioa_gpiohs: gpiohs { + 1 { + function = "GPIOHS1"; + pins = "IO_6"; + }; + 2 { + function = "GPIOHS2"; + pins = "IO_7"; + }; + 3 { + function = "GPIOHS3"; + pins = "IO_17"; + }; + 4 { + function = "GPIOHS4"; + pins = "IO_21"; + }; + 5 { + function = "GPIOHS5"; + pins = "IO_22"; + }; + 6 { + function = "GPIOHS6"; + pins = "IO_23"; + }; + 7 { + function = "GPIOHS7"; + pins = "IO_24"; + }; + 8 { + function = "GPIOHS8"; + pins = "IO_25"; + }; + 9 { + function = "GPIOHS9"; + pins = "IO_30"; + }; + 10 { + function = "GPIOHS10"; + pins = "IO_31"; + }; + 11 { + function = "GPIOHS11"; + pins = "IO_32"; + }; + 12 { + function = "GPIOHS12"; + pins = "IO_33"; + }; + 13 { + function = "GPIOHS13"; + pins = "IO_34"; + }; + 14 { + function = "GPIOHS14"; + pins = "IO_35"; + }; + }; + + fpioa_gpio: gpio { + 0 { + function = "GPIO0"; + pins = "IO_8"; + }; + 1 { + function = "GPIO1"; + pins = "IO_9"; + }; + 2 { + function = "GPIO2"; + pins = "IO_10"; + }; + 3 { + function = "GPIO3"; + pins = "IO_11"; + }; + 4 { + function = "GPIO4"; + pins = "IO_12"; + }; + 5 { + function = "GPIO5"; + pins = "IO_13"; + }; + 6 { + function = "GPIO6"; + pins = "IO_14"; + }; + 7 { + function = "GPIO7"; + pins = "IO_15"; + }; + }; + + fpioa_i2s0: i2s0 { + bck { + function = "I2S0_SCLK"; + pins = "IO_18"; + }; + ws { + function = "I2S0_WS"; + pins = "IO_19"; + }; + dat { + function = "I2S0_IN_D0"; + pins = "IO_20"; + }; + }; + + fpioa_dvp: dvp { + sda { + function = "SCCP_SDA"; + pins = "IO_40"; + }; + sck { + function = "SCCP_SCLK"; + pins = "IO_41"; + }; + rst { + function = "DVP_RST"; + pins = "IO_42"; + }; + vsync { + function = "DVP_VSYNC"; + pins = "IO_43"; + }; + pwdn { + function = "DVP_PWDN"; + pins = "IO_44"; + }; + hsync { + function = "DVP_HSYNC"; + pins = "IO_45"; + }; + xclk { + function = "DVP_XCLK"; + pins = "IO_46"; + }; + pclk { + function = "DVP_PCLK"; + pins = "IO_47"; + }; + }; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; }; diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 8b3b872e2f..0192ce5eae 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -230,6 +230,14 @@ interrupts = <23>; gpio-controller; snps,nr-gpios = <8>; + + isp { + gpio-hog; + gpios = <0 0>; + input; + pinctrl-0 = <&fpioa_isp>; + pinctrl-names = "default"; + }; }; }; @@ -290,11 +298,6 @@ clocks = <&sysclk K210_CLK_SPI2>; resets = <&sysrst K210_RST_SPI2>; spi-max-frequency = <25000000>; - /* - * Likely not the only offset change, but this - * is the only one which is documented. - */ - snps,tmod-offset = <8>; status = "disabled"; }; @@ -372,7 +375,37 @@ reg = <0x502B0000 0x100>; clocks = <&sysclk K210_CLK_FPIOA>; resets = <&sysrst K210_RST_FPIOA>; + kendryte,sysctl = <&sysctl>; + kendryte,power-offset = ; + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; status = "disabled"; + + fpioa_jtag: jtag { + tck { + function = "JTAG_TCLK"; + pins = "IO_0"; + }; + tdi { + function = "JTAG_TDI"; + pins = "IO_1"; + }; + tms { + function = "JTAG_TMS"; + pins = "IO_2"; + }; + tdo { + function = "JTAG_TDO"; + pins = "IO_3"; + }; + }; + + fpioa_isp: isp { + isp { + function = "GPIOHS0"; + pins = "IO_16"; + }; + }; }; sha256: sha256 at 502C0000 {