From patchwork Thu Mar 5 18:53:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 243256 List-Id: U-Boot discussion From: seanga2 at gmail.com (Sean Anderson) Date: Thu, 5 Mar 2020 13:53:28 -0500 Subject: [PATCH v1 8/8] riscv: Add FPIOA and GPIO support for Kendryte K210 In-Reply-To: <20200305185328.951011-1-seanga2@gmail.com> References: <20200305185328.951011-1-seanga2@gmail.com> Message-ID: <20200305185328.951011-9-seanga2@gmail.com> This patch adds the necessary configs and docs for FPIOA and GPIO support on the K210. Signed-off-by: Sean Anderson --- board/sipeed/maix/Kconfig | 12 ++++++++ doc/board/sipeed/maix.rst | 64 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index 8292089fc9..a5a095d4ff 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -27,6 +27,9 @@ config NR_CPUS config NR_DRAM_BANKS default 3 +config SF_DEFAULT_BUS + default 3 + config BOARD_SPECIFIC_OPTIONS def_bool y select GENERIC_RISCV @@ -45,4 +48,13 @@ config BOARD_SPECIFIC_OPTIONS imply RESET_SYSCON imply SYSRESET imply SYSRESET_SYSCON + imply PINCTRL + imply PINCONF + imply PINCTRL_K210 + imply DM_GPIO + imply DWAPB_GPIO + imply SIFIVE_GPIO + imply CMD_GPIO + imply LED + imply LED_GPIO endif diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst index b11ee0182e..312da1e7bb 100644 --- a/doc/board/sipeed/maix.rst +++ b/doc/board/sipeed/maix.rst @@ -132,7 +132,7 @@ To run legacy images, use the ``bootm`` command: Load Address: 80000000 Entry Point: 80000000 - $ picocom -b 115200 /dev/ttyUSB0i + $ picocom -b 115200 /dev/ttyUSB0 => loady ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... C @@ -163,6 +163,66 @@ To run legacy images, use the ``bootm`` command: argv[0] = "" Hit any key to exit ... +Pin Assignment +-------------- + +The K210 contains a Fully Programmable I/O Array (FPIOA), which can remap any of +its 256 input functions to any any of 48 output pins. The following table has +the default pin assignments for the BitM. + +===== ========== ======= +Pin Function Comment +===== ========== ======= +IO_0 JTAG_TCLK +IO_1 JTAG_TDI +IO_2 JTAG_TMS +IO_3 JTAG_TDO +IO_4 UARTHS_RX +IO_5 UARTHS_TX +IO_6 GPIOHS_1 +IO_7 GPIOHS_2 +IO_8 GPIO_0 +IO_9 GPIO_1 +IO_10 GPIO_2 +IO_11 GPIO_3 +IO_12 GPIO_4 Green LED +IO_13 GPIO_5 Red LED +IO_14 GPIO_6 Blue LED +IO_15 GPIO_7 +IO_16 GPIOHS_0 ISP +IO_17 GPIOHS_3 +IO_18 I2S0_SCLK MIC CLK +IO_19 I2S0_WS MIC WS +IO_20 I2S0_IN_D0 MIC SD +IO_21 GPIOHS_4 +IO_22 GPIOHS_5 +IO_23 GPIOHS_6 +IO_24 GPIOHS_7 +IO_25 GPIOHS_8 +IO_26 SPI1_D1 MMC MISO +IO_27 SPI1_SCLK MMC CLK +IO_28 SPI1_D0 MMC MOSI +IO_29 GPIOHS_31 MMC CS +IO_30 GPIOHS_9 +IO_31 GPIOHS_10 +IO_32 GPIOHS_11 +IO_33 GPIOHS_12 +IO_34 GPIOHS_13 +IO_35 GPIOHS_14 +IO_36 GPIOHS_28 Panel CS +IO_37 GPIOHS_29 Panel RST +IO_38 GPIOHS_30 Panel DC +IO_39 SPI0_SCK Panel WR +IO_40 SCCP_SDA +IO_41 SCCP_SCLK +IO_42 DVP_RST +IO_43 DVP_VSYNC +IO_44 DVP_PWDN +IO_45 DVP_HSYNC +IO_46 DVP_XCLK +IO_47 DVP_PCLK +===== ========== ======= + Over- and Under-clocking ------------------------ @@ -294,5 +354,5 @@ Address Size Description 0x8801C000 0x1000 riscv priv spec 1.9 config 0x8801D000 0x2000 flattened device tree (contains only addresses and interrupts) -0x8801f000 0x1000 credits +0x8801F000 0x1000 credits ========== ========= ===========