From patchwork Thu Mar 19 05:38:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiqiang Hou X-Patchwork-Id: 243898 List-Id: U-Boot discussion From: Zhiqiang.Hou at nxp.com (Zhiqiang Hou) Date: Thu, 19 Mar 2020 13:38:39 +0800 Subject: [PATCH 05/12] board: lx2160a: Make sure the RD tables address align to 64KB In-Reply-To: <20200319053846.2304-1-Zhiqiang.Hou@nxp.com> References: <20200319053846.2304-1-Zhiqiang.Hou@nxp.com> Message-ID: <20200319053846.2304-6-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang As the lower 16bit of the redistributor pending table is reserved for describing the memory attributes, we must give a 64KB aligned address to the GIC LPI initialization function. Signed-off-by: Hou Zhiqiang --- board/freescale/lx2160a/lx2160a.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 30b18a75c5..f38c45ada5 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -663,7 +664,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #ifdef CONFIG_GIC_V3_ITS - gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); if (!ret) { if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))