From patchwork Sat Mar 28 03:02:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244442 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Sat, 28 Mar 2020 04:02:06 +0100 Subject: [PATCH] ARM: dts: stm32: Adjust PLL4 settings on AV96 Message-ID: <20200328030206.599938-1-marex@denx.de> The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 70b35e79e5..02dad81b0b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -122,11 +122,11 @@ u-boot,dm-pre-reloc; }; - /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ + /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ pll4: st,pll at 3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 1 39 3 11 4 PQR(1,1,1) >; + cfg = < 1 49 5 11 5 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; };