From patchwork Mon Mar 30 23:12:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 244575 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Mon, 30 Mar 2020 17:12:41 -0600 Subject: [PATCH v3 05/29] tpm: cr50: Use the correct GPIO binding In-Reply-To: <20200330231305.130488-1-sjg@chromium.org> References: <20200330231305.130488-1-sjg@chromium.org> Message-ID: <20200330171226.v3.5.Iffff549a1b63fedb9e8ec87cdc5e9e28478a4587@changeid> This device should use ready-gpios rather than ready-gpio. Fix it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: None arch/x86/dts/chromebook_coral.dts | 2 +- doc/device-tree-bindings/gpio/intel,apl-gpio.txt | 2 +- .../interrupt-controller/intel,acpi-gpe.txt | 2 +- drivers/tpm/cr50_i2c.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index af52e11c89a..d48ef3573ec 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -292,7 +292,7 @@ reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; - ready-gpio = <&gpio_n 28 GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe 0x3c 0>; }; }; diff --git a/doc/device-tree-bindings/gpio/intel,apl-gpio.txt b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt index cf0659b70ec..8422ff63abd 100644 --- a/doc/device-tree-bindings/gpio/intel,apl-gpio.txt +++ b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt @@ -47,7 +47,7 @@ Example: reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; - ready-gpio = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>; }; }; diff --git a/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt b/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt index d9252bf29f7..2fe02d8a227 100644 --- a/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt +++ b/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt @@ -25,6 +25,6 @@ Example: tpm at 50 { reg = <0x50>; compatible = "google,cr50"; - ready-gpio = <&gpio_n 0x1c GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n 0x1c GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe 0x3c 0>; }; diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index c1d2d2fa381..b67051af26a 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -607,7 +607,7 @@ static int cr50_i2c_ofdata_to_platdata(struct udevice *dev) priv->irq = irq; priv->use_irq = true; } else { - ret = gpio_request_by_name(dev, "ready-gpio", 0, + ret = gpio_request_by_name(dev, "ready-gpios", 0, &priv->ready_gpio, GPIOD_IS_IN); if (ret) { log_warning("Cr50 does not have an ready GPIO/interrupt (err=%d)\n",