diff mbox series

[1/7] ddr: altera: arria10: Fix incorrect address for mpu1

Message ID 20200415090030.128489-2-ley.foon.tan@intel.com
State Superseded
Headers show
Series ddr: altera: arria10: Convert SDRAM driver to DM | expand

Commit Message

Tan, Ley Foon April 15, 2020, 9 a.m. UTC
Remove extra "SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS" in mpu1 address.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
---
 drivers/ddr/altera/sdram_arria10.c | 1 -
 1 file changed, 1 deletion(-)

Comments

Marek Vasut April 15, 2020, 12:37 p.m. UTC | #1
On 4/15/20 11:00 AM, Ley Foon Tan wrote:
> Remove extra "SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS" in mpu1 address.

I see what the patch does from the patch itself, but the commit message
does not explain _why_ the patch does it. Can you add it ?

[...]
Tan, Ley Foon April 16, 2020, 1:23 a.m. UTC | #2
> -----Original Message-----
> From: Marek Vasut <marex at denx.de>
> Sent: Wednesday, April 15, 2020 8:38 PM
> To: Tan, Ley Foon <ley.foon.tan at intel.com>; u-boot at lists.denx.de
> Cc: Ley Foon Tan <lftan.linux at gmail.com>; See, Chin Liang
> <chin.liang.see at intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>
> Subject: Re: [PATCH 1/7] ddr: altera: arria10: Fix incorrect address for mpu1
> 
> On 4/15/20 11:00 AM, Ley Foon Tan wrote:
> > Remove extra "SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS" in mpu1
> address.
> 
> I see what the patch does from the patch itself, but the commit message
> does not explain _why_ the patch does it. Can you add it ?
> 
> [...]

Okay.

Regards
Ley Foon
diff mbox series

Patch

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 2fd50b7ae550..e0779b810fdc 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -470,7 +470,6 @@  const struct firewall_entry firewall_table[] = {
 	},
 	{
 		"mpu1",
-		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK