From patchwork Wed Jun 24 10:41:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 242850 List-Id: U-Boot discussion From: seanga2 at gmail.com (Sean Anderson) Date: Wed, 24 Jun 2020 06:41:17 -0400 Subject: [PATCH v14 12/20] riscv: Clear pending interrupts before enabling IPIs In-Reply-To: <20200624104125.363509-1-seanga2@gmail.com> References: <20200624104125.363509-1-seanga2@gmail.com> Message-ID: <20200624104125.363509-13-seanga2@gmail.com> On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen --- Changes in v7: - Split of into its own patch arch/riscv/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5f1c220e0c..f408e41ab9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,6 +65,8 @@ _start: #else li t0, SIE_SSIE #endif + /* Clear any pending IPIs */ + csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif