From patchwork Fri Jul 10 12:55:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 241311 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (Chee Hong Ang) Date: Fri, 10 Jul 2020 20:55:21 +0800 Subject: [PATCH v1 2/4] clk: agilex: Add clock enable support In-Reply-To: <20200710125523.68008-1-chee.hong.ang@intel.com> References: <20200710125523.68008-1-chee.hong.ang@intel.com> Message-ID: <20200710125523.68008-3-chee.hong.ang@intel.com> From: Ley Foon Tan Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- drivers/clk/altera/clk-agilex.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 2ef9292f93..b5cf187364 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -542,6 +542,11 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } } +static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + static int socfpga_clk_probe(struct udevice *dev) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -565,6 +570,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) } static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, .get_rate = socfpga_clk_get_rate, };