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Tue, 29 Jun 2021 01:59:23 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V2 05/46] imx: imx8ulp: add get reset cause Date: Tue, 29 Jun 2021 10:31:59 +0800 Message-Id: <20210629023240.22394-6-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210629023240.22394-1-peng.fan@oss.nxp.com> References: <20210629023240.22394-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0088.apcprd06.prod.outlook.com (2603:1096:3:14::14) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0088.apcprd06.prod.outlook.com (2603:1096:3:14::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.19 via Frontend Transport; Tue, 29 Jun 2021 01:59:21 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4167a9eb-ea92-425c-5d40-08d93aa18414 X-MS-TrafficTypeDiagnostic: DB7PR04MB4633: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:93; 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Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 69 +++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) -- 2.30.0 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e6ac5f8d25..383dbe6000 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -32,6 +32,73 @@ enum bt_mode get_boot_mode(void) return LOW_POWER_BOOT; } +#define CMC_SRS_TAMPER BIT(31) +#define CMC_SRS_SECURITY BIT(30) +#define CMC_SRS_TZWDG BIT(29) +#define CMC_SRS_JTAG_RST BIT(28) +#define CMC_SRS_CORE1 BIT(16) +#define CMC_SRS_LOCKUP BIT(15) +#define CMC_SRS_SW BIT(14) +#define CMC_SRS_WDG BIT(13) +#define CMC_SRS_PIN_RESET BIT(8) +#define CMC_SRS_WARM BIT(4) +#define CMC_SRS_HVD BIT(3) +#define CMC_SRS_LVD BIT(2) +#define CMC_SRS_POR BIT(1) +#define CMC_SRS_WUP BIT(0) + +static u32 reset_cause = -1; + +static char *get_reset_cause(char *ret) +{ + u32 cause1, cause = 0, srs = 0; + void __iomem *reg_ssrs = (void __iomem *)(SRC_BASE_ADDR + 0x88); + void __iomem *reg_srs = (void __iomem *)(SRC_BASE_ADDR + 0x80); + + if (!ret) + return "null"; + + srs = readl(reg_srs); + cause1 = readl(reg_ssrs); + + reset_cause = cause1; + + cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); + + switch (cause) { + case CMC_SRS_POR: + sprintf(ret, "%s", "POR"); + break; + case CMC_SRS_WUP: + sprintf(ret, "%s", "WUP"); + break; + case CMC_SRS_WARM: + cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | + CMC_SRS_JTAG_RST); + switch (cause) { + case CMC_SRS_WDG: + sprintf(ret, "%s", "WARM-WDG"); + break; + case CMC_SRS_SW: + sprintf(ret, "%s", "WARM-SW"); + break; + case CMC_SRS_JTAG_RST: + sprintf(ret, "%s", "WARM-JTAG"); + break; + default: + sprintf(ret, "%s", "WARM-UNKN"); + break; + } + break; + default: + sprintf(ret, "%s-%X", "UNKN", cause1); + break; + } + + debug("[%X] SRS[%X] %X - ", cause1, srs, srs ^ cause1); + return ret; +} + #if defined(CONFIG_DISPLAY_CPUINFO) const char *get_imx_type(u32 imxtype) { @@ -50,6 +117,8 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause(cause)); + printf("Boot mode: "); switch (get_boot_mode()) { case LOW_POWER_BOOT: