From patchwork Sun Oct 2 23:51:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jassi Brar X-Patchwork-Id: 611758 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp826734pvb; Sun, 2 Oct 2022 16:51:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6y25cDFLFjEFr2JouVB3pQ9qEZ9jdHwopA+aeQ7/ULA3/LNUXKgGnIgYziSfoH9JIJhkaf X-Received: by 2002:a05:6402:5507:b0:452:183f:16d1 with SMTP id fi7-20020a056402550700b00452183f16d1mr16823839edb.96.1664754706865; Sun, 02 Oct 2022 16:51:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664754706; cv=none; d=google.com; s=arc-20160816; b=T0g1d3cotHXsLG7/XV7g+y45KvnZcSFddG+lUIxWgBZPEEDj9sHKEqHDnQmc9gs4OO cvEAOKS4660FOES54NnKPd4Vx2PEglPNA8p7Fi+KM6froGdzXPTNUGF/MBtmB1nVbGHq SgRI8GRzA2tjX2spEDj6UN5JYgN53/wzL9A9VEmcNn3xGfCNk58om+pNr4X+SEp8S6BG 7YxxUE0+SQgz6nWUfmKewFiPeWsarVaepoxb8vOZ8vFEJx+IOSHhgCFH6BUHtnnpGIIO t74Rx3kcdiYTHNpnxQ9uNQb7uhu/TnpBAOMhBGQgvCF1Oqrcczxg+kHVXtRWn6nvrIDP AFaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LtyKn9yIHqzbMBgWN3x4LJwRiRWZm5yM4WxPv2l46Sk=; b=W3B+uJ6fSFg3FGuca9PBX7T+eq+XXWu7FAfyJcICQ653f6Hv1gdg4yEIRdqZdrYmwd uT45/qem1Bk1au5//vldE0A8wVRd1K/5u9aw5kHD13IYndV7s54nZTmGKkb0Xz/kz0zA 2Y9bu5cO4eYq7NmG0HhEKeuBuVbKgU+oy46tp/kxlo/jlp9p5SOuGZIAYZgJA0aoJgwy Jfpg566KBvLZSAH/CGEcD12yvwrPdXWsmUVSPSGfJDVZHF01/qov7Da2yE1aW+JYNQRD pEBM1hzdjuFxMf6Yir7ec3LnKDAFBfLTcc3j5mCzSMewNNpz+WtawgWdETNidbEDS2hs mGWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=dG+UuAi7; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id ne5-20020a1709077b8500b00781b6ce15e1si6905929ejc.101.2022.10.02.16.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 16:51:46 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=dG+UuAi7; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DED50847F4; Mon, 3 Oct 2022 01:51:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="dG+UuAi7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E1DBC8447D; Mon, 3 Oct 2022 01:51:43 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd31.google.com (mail-io1-xd31.google.com [IPv6:2607:f8b0:4864:20::d31]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C837C84BB9 for ; Mon, 3 Oct 2022 01:51:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jassisinghbrar@gmail.com Received: by mail-io1-xd31.google.com with SMTP id g8so7050524iob.0 for ; Sun, 02 Oct 2022 16:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=LtyKn9yIHqzbMBgWN3x4LJwRiRWZm5yM4WxPv2l46Sk=; b=dG+UuAi7Hr9GezSsyZqArxUlyaracDkOz0WuTpI9SfQPWMVeD+LhdlV/Vd63iN4/6p MsmgF3s9uyrnGl1IfRJtdduFfsbWaUFbLPaTw6hrlv1FybwJeA+Gc5a7rBdrCIBg3AqT xz8P+eFn1kbilEUvJFHzfmMbFeCHM+7suXwHtYIuAy/tE2q9BpvUw7oWujtasQNLnvMw yJ3cW414JRNY5xxaRrDPcYullYBw5IytdHXfl9LeSLfd2hJL6i/UldJxohOWQ51+stFE KwTpgSSwsl7QgGxEz3QgCIm7CpCACs5MmJzzFzcEtmBr3xBFKW5pfnSlYW25fuqsiua0 Tkow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=LtyKn9yIHqzbMBgWN3x4LJwRiRWZm5yM4WxPv2l46Sk=; b=huGAj4Kqy/Q9cOzKRZLJ1eITHqbv5epxaXRP/+S0bI01oaOFyB5fc2+4vn+AgRpLXD C8a8+5W/1CFiRKgsVYPiOkGGwJBvgeiWtZZaxSNUJnJVlLUmt0+8ipDF7Or+BHgD7E2I 6vnNL1YrxqzJSs2/R4PuwWhZF7gxr1bZ08IeI/IeHqAeR146MgfMJfMK3HzP3J5+Jmw/ qGKdJOHGTklyql6IWitCoj82DspedHhhVoXL9Qs43SlVImWL/+dIFzZFF0rCPZXOZJpo r2YhEsq6gVtv85/gheSacrxgu7h8Yh/cDYtdDgAMUa16axxwjHdk+iJssBcPNHEvSTaz rVeA== X-Gm-Message-State: ACrzQf2MwhPwohjg6cDbh25q16ADSr5oULhgz6/5UUSCZx1UEAwoGwUV 2Y1OOsRjcZNraXinmpWtH2Ex2hQFjqg= X-Received: by 2002:a05:6638:4304:b0:343:5953:5fc8 with SMTP id bt4-20020a056638430400b0034359535fc8mr9003014jab.123.1664754697721; Sun, 02 Oct 2022 16:51:37 -0700 (PDT) Received: from localhost.localdomain (wnpgmb0311w-ds01-45-179-115.dynamic.bellmts.net. [206.45.179.115]) by smtp.gmail.com with ESMTPSA id c18-20020a0566022d1200b006a262317411sm3878213iow.35.2022.10.02.16.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 16:51:37 -0700 (PDT) From: jassisinghbrar@gmail.com To: u-boot@lists.denx.de Cc: xypron.glpk@gmx.de, ilias.apalodimas@linaro.org, takahiro.akashi@linaro.org, sjg@chromium.org, trini@konsulko.com, etienne.carriere@linaro.org, monstr@monstr.eu, Sughosh Ganu , Jassi Brar Subject: [PATCHv2 1/5] FWU: Add FWU metadata access driver for MTD storage regions Date: Sun, 2 Oct 2022 18:51:32 -0500 Message-Id: <20221002235132.344240-1-jassisinghbrar@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221002235046.344149-1-jassisinghbrar@gmail.com> References: <20221002235046.344149-1-jassisinghbrar@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Sughosh Ganu In the FWU Multi Bank Update feature, the information about the updatable images is stored as part of the metadata, on a separate region. Add a driver for reading from and writing to the metadata when the updatable images and the metadata are stored on a raw MTD region. Signed-off-by: Sughosh Ganu Signed-off-by: Jassi Brar --- drivers/fwu-mdata/Kconfig | 17 +- drivers/fwu-mdata/Makefile | 1 + drivers/fwu-mdata/raw_mtd.c | 305 ++++++++++++++++++++++++++++++++++++ 3 files changed, 322 insertions(+), 1 deletion(-) create mode 100644 drivers/fwu-mdata/raw_mtd.c diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig index 36c4479a59..841c6f5b2d 100644 --- a/drivers/fwu-mdata/Kconfig +++ b/drivers/fwu-mdata/Kconfig @@ -6,11 +6,26 @@ config FWU_MDATA FWU Metadata partitions reside on the same storage device which contains the other FWU updatable firmware images. +choice + prompt "Storage Layout Scheme" + depends on FWU_MDATA + default FWU_MDATA_GPT_BLK + config FWU_MDATA_GPT_BLK - bool "FWU Metadata access for GPT partitioned Block devices" + bool "GPT Partitioned Block devices" select PARTITION_TYPE_GUID select PARTITION_UUIDS depends on FWU_MDATA && BLK && EFI_PARTITION help Enable support for accessing FWU Metadata on GPT partitioned block devices. + +config FWU_MDATA_MTD + bool "Raw MTD devices" + depends on MTD + help + Enable support for accessing FWU Metadata on non-partitioned + (or non-GPT partitioned, e.g. partition nodes in devicetree) + MTD devices. + +endchoice diff --git a/drivers/fwu-mdata/Makefile b/drivers/fwu-mdata/Makefile index 3fee64c10c..06c49747ba 100644 --- a/drivers/fwu-mdata/Makefile +++ b/drivers/fwu-mdata/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_FWU_MDATA) += fwu-mdata-uclass.o obj-$(CONFIG_FWU_MDATA_GPT_BLK) += gpt_blk.o +obj-$(CONFIG_FWU_MDATA_MTD) += raw_mtd.o diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c new file mode 100644 index 0000000000..ff2064b442 --- /dev/null +++ b/drivers/fwu-mdata/raw_mtd.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_FWU_MDATA + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Internal helper structure to move data around */ +struct fwu_mdata_mtd_priv { + struct mtd_info *mtd; + u32 pri_offset; + u32 sec_offset; +}; + +enum fwu_mtd_op { + FWU_MTD_READ, + FWU_MTD_WRITE, +}; + +#define FWU_MDATA_PRIMARY true +#define FWU_MDATA_SECONDARY false + +static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size) +{ + return !do_div(size, mtd->erasesize); +} + +static int mtd_io_data(struct mtd_info *mtd, u32 offs, u32 size, void *data, + enum fwu_mtd_op op) +{ + struct mtd_oob_ops io_op ={}; + u64 lock_offs, lock_len; + size_t len; + void *buf; + int ret; + + if (!mtd_is_aligned_with_block_size(mtd, offs)) { + log_err("Offset unaligned with a block (0x%x)\n", mtd->erasesize); + return -EINVAL; + } + + lock_offs = offs; + /* This will expand erase size to align with the block size */ + lock_len = round_up(size, mtd->erasesize); + + ret = mtd_unlock(mtd, lock_offs, lock_len); + if (ret && ret != -EOPNOTSUPP) + return ret; + + if (op == FWU_MTD_WRITE) { + struct erase_info erase_op = {}; + + erase_op.mtd = mtd; + erase_op.addr = lock_offs; + erase_op.len = lock_len; + erase_op.scrub = 0; + + ret = mtd_erase(mtd, &erase_op); + if (ret) + goto lock; + } + + /* Also, expand the write size to align with the write size */ + len = round_up(size, mtd->writesize); + + buf = memalign(ARCH_DMA_MINALIGN, len); + if (!buf) { + ret = -ENOMEM; + goto lock; + } + memset(buf, 0xff, len); + + io_op.mode = MTD_OPS_AUTO_OOB; + io_op.len = len; + io_op.ooblen = 0; + io_op.datbuf = buf; + io_op.oobbuf = NULL; + + if (op == FWU_MTD_WRITE) { + memcpy(buf, data, size); + ret = mtd_write_oob(mtd, offs, &io_op); + } else { + ret = mtd_read_oob(mtd, offs, &io_op); + if (!ret) + memcpy(data, buf, size); + } + free(buf); + +lock: + mtd_lock(mtd, lock_offs, lock_len); + + return ret; +} + +static int fwu_mtd_load_mdata(struct mtd_info *mtd, struct fwu_mdata *mdata, + u32 offs, bool primary) +{ + size_t size = sizeof(struct fwu_mdata); + int ret; + + ret = mtd_io_data(mtd, offs, size, mdata, FWU_MTD_READ); + if (ret >= 0) + ret = fwu_verify_mdata(mdata, primary); + + return ret; +} + +static int fwu_mtd_save_primary_mdata(struct fwu_mdata_mtd_priv *mtd_priv, + struct fwu_mdata *mdata) +{ + return mtd_io_data(mtd_priv->mtd, mtd_priv->pri_offset, + sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE); +} + +static int fwu_mtd_save_secondary_mdata(struct fwu_mdata_mtd_priv *mtd_priv, + struct fwu_mdata *mdata) +{ + return mtd_io_data(mtd_priv->mtd, mtd_priv->sec_offset, + sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE); +} + +static int fwu_mtd_get_valid_mdata(struct fwu_mdata_mtd_priv *mtd_priv, + struct fwu_mdata *mdata) +{ + int ret; + + ret = fwu_mtd_load_mdata(mtd_priv->mtd, mdata, + mtd_priv->pri_offset, FWU_MDATA_PRIMARY); + if (!ret) + return 0; + + log_debug("Failed to load primary mdata. Trying secondary...\n"); + + ret = fwu_mtd_load_mdata(mtd_priv->mtd, mdata, + mtd_priv->sec_offset, FWU_MDATA_SECONDARY); + if (ret) { + log_debug("Failed to load secondary mdata.\n"); + return -1; + } + + return 0; +} + +static int fwu_mtd_update_mdata(struct udevice *dev, struct fwu_mdata *mdata) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + int ret; + + /* First write the primary mdata */ + ret = fwu_mtd_save_primary_mdata(mtd_priv, mdata); + if (ret < 0) { + log_debug("Failed to update the primary mdata.\n"); + return ret; + } + + /* And now the replica */ + ret = fwu_mtd_save_secondary_mdata(mtd_priv, mdata); + if (ret < 0) { + log_debug("Failed to update the secondary mdata.\n"); + return ret; + } + + return 0; +} + +static int fwu_mtd_check_mdata(struct udevice *dev) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + struct fwu_mdata primary, secondary; + bool pri = false, sec = false; + int ret; + + ret = fwu_mtd_load_mdata(mtd_priv->mtd, &primary, + mtd_priv->pri_offset, FWU_MDATA_PRIMARY); + if (ret < 0) + log_debug("Failed to read the primary mdata: %d\n", ret); + else + pri = true; + + ret = fwu_mtd_load_mdata(mtd_priv->mtd, &secondary, + mtd_priv->sec_offset, FWU_MDATA_SECONDARY); + if (ret < 0) + log_debug("Failed to read the secondary mdata: %d\n", ret); + else + sec = true; + + if (pri && sec) { + if (memcmp(&primary, &secondary, sizeof(struct fwu_mdata))) { + log_debug("The primary and the secondary mdata are different\n"); + ret = -1; + } + } else if (pri) { + ret = fwu_mtd_save_secondary_mdata(mtd_priv, &primary); + if (ret < 0) + log_debug("Restoring secondary mdata partition failed\n"); + } else if (sec) { + ret = fwu_mtd_save_primary_mdata(mtd_priv, &secondary); + if (ret < 0) + log_debug("Restoring primary mdata partition failed\n"); + } + + return ret; +} + +static int fwu_mtd_get_mdata(struct udevice *dev, struct fwu_mdata *mdata) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + + return fwu_mtd_get_valid_mdata(mtd_priv, mdata); +} + +/** + * fwu_mdata_mtd_of_to_plat() - Translate from DT to fwu mdata device + */ +static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + const fdt32_t *phandle_p = NULL; + struct udevice *mtd_dev; + struct mtd_info *mtd; + int ret, size; + u32 phandle; + + /* Find the FWU mdata storage device */ + phandle_p = ofnode_get_property(dev_ofnode(dev), + "fwu-mdata-store", &size); + if (!phandle_p) { + log_err("FWU meta data store not defined in device-tree\n"); + return -ENOENT; + } + + phandle = fdt32_to_cpu(*phandle_p); + + ret = device_get_global_by_ofnode(ofnode_get_by_phandle(phandle), + &mtd_dev); + if (ret) { + log_err("FWU: failed to get mtd device\n"); + return ret; + } + + mtd_probe_devices(); + + mtd_for_each_device(mtd) { + if (mtd->dev == mtd_dev) { + mtd_priv->mtd = mtd; + log_debug("Found the FWU mdata mtd device %s\n", mtd->name); + break; + } + } + if (!mtd_priv->mtd) { + log_err("Failed to find mtd device by fwu-mdata-store\n"); + return -ENOENT; + } + + /* Get the offset of primary and seconday mdata */ + ret = ofnode_read_u32_index(dev_ofnode(dev), "mdata-offsets", 0, + &mtd_priv->pri_offset); + if (ret) + return ret; + ret = ofnode_read_u32_index(dev_ofnode(dev), "mdata-offsets", 1, + &mtd_priv->sec_offset); + if (ret) + return ret; + + return 0; +} + +static int fwu_mdata_mtd_probe(struct udevice *dev) +{ + /* Ensure the metadata can be read. */ + return fwu_mtd_check_mdata(dev); +} + +static struct fwu_mdata_ops fwu_mtd_ops = { + .check_mdata = fwu_mtd_check_mdata, + .get_mdata = fwu_mtd_get_mdata, + .update_mdata = fwu_mtd_update_mdata, +}; + +static const struct udevice_id fwu_mdata_ids[] = { + { .compatible = "u-boot,fwu-mdata-mtd" }, + { } +}; + +U_BOOT_DRIVER(fwu_mdata_mtd) = { + .name = "fwu-mdata-mtd", + .id = UCLASS_FWU_MDATA, + .of_match = fwu_mdata_ids, + .ops = &fwu_mtd_ops, + .probe = fwu_mdata_mtd_probe, + .of_to_plat = fwu_mdata_mtd_of_to_plat, + .priv_auto = sizeof(struct fwu_mdata_mtd_priv), +};