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([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:18 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 01/14] qcs404: sysmap: Don't map reserved memory ranges Date: Wed, 1 Feb 2023 19:28:48 +0530 Message-Id: <20230201135901.482671-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Currently u-boot maps whole of 1G RAM but there reserved memory ranges on QCS404 which are reserved for TrustZone, various firmware components etc. Any access to these reserved memory ranges causes a bus hang issue. So disable mapping for reserved memory ranges in u-boot. Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/sysmap-qcs404.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c index b7409031a0..64ca4adf1b 100644 --- a/arch/arm/mach-snapdragon/sysmap-qcs404.c +++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c @@ -19,7 +19,19 @@ static struct mm_region qcs404_mem_map[] = { }, { .virt = 0x80000000UL, /* DDR */ .phys = 0x80000000UL, /* DDR */ - .size = 0x40000000UL, + .size = 0x05900000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x89600000UL, /* DDR */ + .phys = 0x89600000UL, /* DDR */ + .size = 0x162000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa0000000UL, /* DDR */ + .phys = 0xa0000000UL, /* DDR */ + .size = 0x20000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, {