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[2.99.112.229]) by smtp.gmail.com with ESMTPSA id l21-20020a056000023500b003198a9d758dsm10682342wrz.78.2023.10.24.13.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 13:23:58 -0700 (PDT) From: Caleb Connolly Date: Tue, 24 Oct 2023 21:23:54 +0100 Subject: [PATCH 3/8] clk/qcom: move ipq4019 driver from mach-ipq40xx MIME-Version: 1.0 Message-Id: <20231024-b4-qcom-clk-v1-3-9d96359b9a82@linaro.org> References: <20231024-b4-qcom-clk-v1-0-9d96359b9a82@linaro.org> In-Reply-To: <20231024-b4-qcom-clk-v1-0-9d96359b9a82@linaro.org> To: Ramon Fried , Lukasz Majewski , Sean Anderson , Bharat Gooty , Rayagonda Kokatanur , Robert Marko , Bhupesh Sharma , Luka Kovacic , Luka Perkov Cc: Vladimir Zapolskiy , u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.13-dev-46309 X-Developer-Signature: v=1; a=openpgp-sha256; l=4011; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=UZxSghk/MVWFH5Z2r7wH04r4JACoSWmLvnYnFE1iCCg=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhlQL9VvH3c/nHDzz+01UgmnQTVabU3btv63/tbep6d9vT o6d9GJnRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZjIvFpGhoWnNSab7Dl1rOSX yMr4AKftK3a/kTrXf9hlxlM33s6rp5Yy/LMT9Hyrxaey5p3fvsDiiGrdwnUFm7sV1veeeJNd43l 6pigA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 1 + arch/arm/mach-ipq40xx/Makefile | 1 - drivers/clk/qcom/Kconfig | 8 +++++ drivers/clk/qcom/Makefile | 1 + .../clk/qcom}/clock-ipq4019.c | 41 ++-------------------- 5 files changed, 12 insertions(+), 40 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 531b081de996..5aaf7e5e32af 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -766,6 +766,7 @@ config ARCH_IPQ40XX select CLK select SMEM select OF_CONTROL + select CLK_QCOM_IPQ4019 imply CMD_DM config ARCH_KEYSTONE diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile index 08a65b8854d3..b36a935c6f9f 100644 --- a/arch/arm/mach-ipq40xx/Makefile +++ b/arch/arm/mach-ipq40xx/Makefile @@ -4,6 +4,5 @@ # # Author: Robert Marko -obj-y += clock-ipq4019.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-ipq4019.o diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a884f077d9b9..0df0d1881a49 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -23,6 +23,14 @@ config CLK_QCOM_APQ8096 on the Snapdragon APQ8096 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_IPQ4019 + bool "Qualcomm IPQ4019 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon IPQ4019 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 44d55583596d..25bd2e1e8bb1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -6,4 +6,5 @@ obj-y += clock-qcom.o obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o +obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipa4019.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c similarity index 56% rename from arch/arm/mach-ipq40xx/clock-ipq4019.c rename to drivers/clk/qcom/clock-ipq4019.c index c1d5c4ecdd81..04c99964df15 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -12,12 +12,9 @@ #include #include #include - #include -struct msm_clk_priv { - phys_addr_t base; -}; +#include "clock-qcom.h" ulong msm_set_rate(struct clk *clk, ulong rate) { @@ -30,23 +27,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate) } } -static int msm_clk_probe(struct udevice *dev) -{ - struct msm_clk_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - - return 0; -} - -static ulong msm_clk_set_rate(struct clk *clk, ulong rate) -{ - return msm_set_rate(clk, rate); -} - -static int msm_enable(struct clk *clk) +int msm_enable(struct clk *clk) { switch (clk->id) { case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ @@ -68,21 +49,3 @@ static int msm_enable(struct clk *clk) } } -static struct clk_ops msm_clk_ops = { - .set_rate = msm_clk_set_rate, - .enable = msm_enable, -}; - -static const struct udevice_id msm_clk_ids[] = { - { .compatible = "qcom,gcc-ipq4019" }, - { } -}; - -U_BOOT_DRIVER(clk_msm) = { - .name = "clk_msm", - .id = UCLASS_CLK, - .of_match = msm_clk_ids, - .ops = &msm_clk_ops, - .priv_auto = sizeof(struct msm_clk_priv), - .probe = msm_clk_probe, -};