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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id g11-20020a05600c310b00b0040f035bebfcsm1799017wmo.12.2024.01.30.06.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 06:05:14 -0800 (PST) From: Caleb Connolly Date: Tue, 30 Jan 2024 14:04:54 +0000 Subject: [PATCH v3 06/36] clock/qcom: qcs404: fix clk_set_rate MIME-Version: 1.0 Message-Id: <20240130-b4-qcom-common-target-v3-6-e523cbf9e556@linaro.org> References: <20240130-b4-qcom-common-target-v3-0-e523cbf9e556@linaro.org> In-Reply-To: <20240130-b4-qcom-common-target-v3-0-e523cbf9e556@linaro.org> To: Neil Armstrong , Sumit Garg , Ramon Fried , Dzmitry Sankouski , Caleb Connolly , Peng Fan , Jaehoon Chung , Rayagonda Kokatanur , Lukasz Majewski , Sean Anderson , Jorge Ramirez-Ortiz , Stephan Gerhold Cc: Marek Vasut , u-boot@lists.denx.de X-Mailer: b4 0.13-dev-4bd13 X-Developer-Signature: v=1; a=openpgp-sha256; l=1160; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=ZOd9uPKxeZ3ipUmnwBb71i0WJ7wJt+3B4De0gEOoyPQ=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhtSdTALcJzIbLdyqkw66XBXWeXf64oK2xbGs07p/eRdtL c5MmpvaUcrCIMjBICumyCJ+Ypll09rL9hrbF1yAmcPKBDKEgYtTACbiP4eRYe9t4w9vSrRYYk62 KOvc2NO/Jykg/MvnYMW4oGP9LB5/eBgZ+lYcjj+1mC9rw06NnzGMtj8+zH9WrSt9nqWAj/NH1Vq 79wA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We should be returning the rate that we set the clock to, drivers like MMC rely on this. So fix it. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-qcs404.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index f5b352803927..03fd65a9328b 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -207,7 +207,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); - break; + return rate; case GCC_SDCC1_AHB_CLK: clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); break; @@ -224,11 +224,10 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); - break; - default: - return 0; + return rate; } + log_warning("Unknown clock id %ld\n", clk->id); return 0; }