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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id e4-20020adfe384000000b0033cfa00e497sm194025wrm.64.2024.02.15.12.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 12:52:30 -0800 (PST) From: Caleb Connolly Date: Thu, 15 Feb 2024 20:52:24 +0000 Subject: [PATCH v4 06/39] clock/qcom: qcs404: fix clk_set_rate MIME-Version: 1.0 Message-Id: <20240215-b4-qcom-common-target-v4-6-ed06355c634a@linaro.org> References: <20240215-b4-qcom-common-target-v4-0-ed06355c634a@linaro.org> In-Reply-To: <20240215-b4-qcom-common-target-v4-0-ed06355c634a@linaro.org> To: Neil Armstrong , Sumit Garg , Ramon Fried , Dzmitry Sankouski , Caleb Connolly , Peng Fan , Jaehoon Chung , Rayagonda Kokatanur , Lukasz Majewski , Sean Anderson , Jorge Ramirez-Ortiz , Stephan Gerhold Cc: Marek Vasut , u-boot@lists.denx.de X-Mailer: b4 0.13-dev-4bd13 X-Developer-Signature: v=1; a=openpgp-sha256; l=2419; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=ar0lMezuSb4HK1JVZdDWZA2XsUzJ0i0dyyeTMLBN20g=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhtRzlS0TO28x3fqW0R3ZFlVn4VUioXdrv0LOxCOFnCoPr e/H1M/pKGVhEORgkBVTZBE/scyyae1le43tCy7AzGFlAhnCwMUpABOZY83wv37mTd169+YyW7uv OdvOrmBRjODY+WieRUx8fPSv39Pc6hgZppSH8iSeYmX40fx2699TlUW9xoHedZtDb/LqVq77yL9 4EwA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We should be returning the rate that we set the clock to, drivers like MMC rely on this. So fix it. Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg --- drivers/clk/qcom/clock-qcs404.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index f5b352803927..958312b88842 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_BLSP1_UART2_APPS_CLK: - /* UART: 115200 */ + /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); - break; - case GCC_BLSP1_AHB_CLK: - clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); - break; + return 1843200; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); - break; - case GCC_SDCC1_AHB_CLK: - clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); - break; + return rate; case GCC_ETH_RGMII_CLK: if (rate == 250000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, @@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); - break; - default: - return 0; + return rate; } + /* There is a bug only seeming to affect this board where the MMC driver somehow calls + * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device. + * The only clock with ID 0 is the xo_board clock which should not be associated with + * this device... + */ + log_debug("Unknown clock id %ld\n", clk->id); return 0; } @@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk) clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, CFG_CLK_SRC_CXO); break; + case GCC_SDCC1_AHB_CLK: + clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); + break; default: return 0; }