From patchwork Fri Apr 5 09:07:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 786208 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1101:b0:343:f27d:c44e with SMTP id z1csp67618wrw; Fri, 5 Apr 2024 02:09:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV86kXz9DKaka7PaPhjnwR9RoKrVxsdWO5W8oQkwZ+bTDDkzDL/uQsfTbRUQfFPhiOnPkUGfdObFmDnHGmvVF06 X-Google-Smtp-Source: AGHT+IH6yplQiw3jzvRApJCqitpbzM9NxqEtjV1zhvs588UaFTDB8zVa9xkVQzIDSg5XhyVzRobd X-Received: by 2002:a17:906:4550:b0:a4d:f553:c652 with SMTP id s16-20020a170906455000b00a4df553c652mr527413ejq.75.1712308146935; Fri, 05 Apr 2024 02:09:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712308146; cv=none; d=google.com; s=arc-20160816; b=V50l7eaPqex7rVBO7k4XcbYlyuJAUXBDr2fMMnc9VuTUGfi7cJ0ulnLzQI3ohZSc3R ZI71/tz3dhxJcJwlLtqv60vCcYUYwFuDXttXXU8E5Fqk7xcvCN/0btya0+OfCPiWU8KP 4yp2Cuhf3lSifW8sfSIP/+xQ50XYsBj9dmuNpp0IlpEqF0z09BqZE6tYc0+NwlMXQuKL /LRcBb1vvLwA8cjUhVH1ks2h/CXDfyuZGch/j/me1sA7cyONbm2UctmIKWwa9gTQrxLV vOm9xw8Dgdj/VCRK3SJhPfNRTHra0sIWunudEvG1cqHm9rz13CgD+BxXm3+TW6cQYKWE Bs1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OQQFm53Y6noFLmaH27wGfZfjy164/8YCVf5iflGTt5w=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=RiYPYD+TJ8l+eJUJnDhYZbaNVdVhPw880Ek/2mwo5vVeoCgfpXHqFMgBXW7beCoHIb mUzKLmsvhWNBPde/0a7kq8RCOihGySaY2arpMZSF0wlORPlBfU2yGP/47rkfpBQ0Q+Ro /QWGP9/okyIILiHgp4EMlBAaWGJxlHEjc+qgroGFQbISlHheHIc/OMvEdiRYV5CFpp5X ja9eDuuZC4VkQgqhhg51zZ0RponTZd4xfQYaCugSdqF83ogqY96ORZVeP3SbhMwnnavm TwQr7Ec6bdrAjTy3sve7zuPExLUtYfgjeR5c55rdMUqKVq3ubkJRlzfxHCO5wvfnX8+x YqSA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sffkqgmh; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id kj26-20020a170907765a00b00a3f6ba0165dsi508672ejc.261.2024.04.05.02.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:09:06 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sffkqgmh; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 20174884F0; Fri, 5 Apr 2024 11:08:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Sffkqgmh"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7DB85884CA; Fri, 5 Apr 2024 11:08:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 63CE5884E6 for ; Fri, 5 Apr 2024 11:08:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1e0ae065d24so16348015ad.1 for ; Fri, 05 Apr 2024 02:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712308124; x=1712912924; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OQQFm53Y6noFLmaH27wGfZfjy164/8YCVf5iflGTt5w=; b=Sffkqgmh/ElZMZhK+Xn6AOTO5IfwQlM0i/YActamxPMwtHQFOxV5Xa3+BZUGU/n1Xe 9F6pU9mFSQguyGtDi1awwZF4pu3Yyyd89XvkJF2BUf1o7ZhUn25yTtMGKK2Yrr5m9vXA jKojawwh8lyIZBAgkKOxNDQmsMYK1186MP8qYTj6r36atOF8g0vHb+PRJRWawae7erCU WytPUzTwGksnN546k2+ozEJb0Ccchu5i9oWm/UL4TJBU/AFEoH2BbCH9uSQGFj3Pg9Ui OyvCFZ1+wnjr233DlPDBNshDp5SYLUHjLI4V1nDPPlYg6tt38icrPOUrSm13k3s1eR7p qoPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712308124; x=1712912924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OQQFm53Y6noFLmaH27wGfZfjy164/8YCVf5iflGTt5w=; b=X5T9CYDTSPkd0iWJGFheW3+wONEwI6wZtmAW0TEW4vCFxkpLHoQ/ySBD0MyVJ6EjVq Rd8gWrmZFdkTkSTskL7avJIqWRif7T6yqNbGTZvN6qYaybahTslp2FVyH8VgDzYzJ/kr jtH/ZSLLXrBI8mAIz5hoXntAwFdhoKiJXBA05YoMtphkZUekzLvelDAG7LhPOjZFjtWy vk0jBtp1F3U4t57YGEExzOHqgMuzzYkiISRm1cFqAOj3BvlQrT/40bAfGP4q1cMg5ue1 h1FvPt6lCv6h4Sm3oiMejVCr2ydFaM2dwtBZKNMcy1MtdrnjZ7IdXBdUy5J1k6o1LYF4 Rtgg== X-Gm-Message-State: AOJu0Yzn2US6bHyf2RHg6X6HMUs2r8Sya0v4uAVMWp6xIvvJt7VM9hGx xIk861Yx2y+DQiCwwCz4XdJoU0eQK5BClq9okRb2JTnrpD97MJYKH8MQmmo9fX1boPIZ5NN2n2n U X-Received: by 2002:a17:902:7449:b0:1e0:7f78:624d with SMTP id e9-20020a170902744900b001e07f78624dmr732533plt.57.1712308124663; Fri, 05 Apr 2024 02:08:44 -0700 (PDT) Received: from sumit-X1.. ([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:44 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 4/6] pinctrl: qcom: Add support for driving GPIO pins output Date: Fri, 5 Apr 2024 14:37:40 +0530 Message-Id: <20240405090742.4148304-5-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for driving the GPIO pins as output low or high. Signed-off-by: Sumit Garg --- drivers/pinctrl/qcom/pinctrl-qcom.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 909e566acf5..e68971b37ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -29,15 +29,24 @@ struct msm_pinctrl_priv { #define GPIO_CONFIG_REG(priv, x) \ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x)) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) +#define GPIO_IN_OUT_REG(priv, x) \ + (GPIO_CONFIG_REG(priv, x) + 0x4) + +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_OUTPUT_MASK BIT(1) +#define TLMM_GPIO_OE_MASK BIT(9) + +/* GPIO register shifts. */ +#define GPIO_OUT_SHIFT 1 static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, }; static int msm_get_functions_count(struct udevice *dev) @@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2); + TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2); return 0; } @@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break; + case PIN_CONFIG_OUTPUT: + writel(argument << GPIO_OUT_SHIFT, + priv->base + GPIO_IN_OUT_REG(priv, pin_selector)); + setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), + TLMM_GPIO_OE_MASK); + break; default: return 0; }