From patchwork Wed Oct 25 17:59:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 117132 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1118948qgn; Wed, 25 Oct 2017 10:59:59 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TN5LdGX8kZjcsHfF2UWGhFPxIkHWGnhw0wb+w9J20wOTk5OPuOrLzDfE4PtXwhyhmYT0iJ X-Received: by 10.159.249.75 with SMTP id h11mr2406159pls.192.1508954399108; Wed, 25 Oct 2017 10:59:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508954399; cv=none; d=google.com; s=arc-20160816; b=uei1+i/aHEDhlQnhEupA0f+FYyzTHI+06KRgk1F+s57L/p5URFXXf2i+NqV6GoTADM 0Hc8DrJzF0Yc5ZPitwpfyGrn+JENNIlhGu0pZqgXil2zJi09NMqE9FNExIy+gM4rQ2xp mtUtQX4DAeJ0n/qIpq6Pe9jg7lmIzzn7hHvk2sc8CLG8ZTQsLkd1Q5l6DmO8ms4DjCj1 QBtc+K7/AFHj+ZpNo/IYigMpoZZus3aMe6HRm0t4lje4BZo7WsIYVBN1xVnrbg8EZusA K0jBXQI2QjWmiwGJE/ZczV5zP/WwNgyp1k1r+L+xQbtEGrRfhKV3obh0oiQ42S+IAySd 28hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :delivered-to:arc-authentication-results; bh=QnFJM3Fg65sgevSZp3VE31dlG00wfv9JbzMb1IZZkCM=; b=DYrkYcLeHxdVONIMZyBj3/nCM1E0Kn+aXjpNk8pOYJXqm8xQAftsB8NVcWzVoCEW7R YRJDs6KclLGlakt1Jlqs6R8Pv3gwHiKNo7uWOwqc23zqes01iT3Q0yke2nC1aD9jv31T T2nH4eBfd4ZSFRwAaug3Opn4VVIz3ASWvrRI7ZFKx8emaIxLWlwAAnbslNaIOBa7Ennp 0TgZCaFGa/yggnTabpYAwriK7kdS8Q2YudnAB18EqJYefc8eun26xdtkGLTk6pAolSFz pZgyW0MI8xYxS4EHOypn3NjJBLtXYmAMH+hw3d+Fy0wt8aJW2jXbiMzreKevkfarJhmQ fAIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=G03RPGpI; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id u125si2126993pgc.776.2017.10.25.10.59.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Oct 2017 10:59:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=G03RPGpI; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B8ED62034CF77; Wed, 25 Oct 2017 10:56:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4740921CEB141 for ; Wed, 25 Oct 2017 10:56:11 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id j15so829497wre.8 for ; Wed, 25 Oct 2017 10:59:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=R1zG/zuBOAUWV8Yn2BOF62J6zPoItYYmv6KFTx1+o64=; b=G03RPGpIf4UH4aC6mjHJpgNv8JTanG+TUB9ReQQBDc7HTgfzVfX7HgzEfdkfyx1UDF clYbT/G9tVlZ4lY3WQtFjVyGceWBwwEbm5Kw0MozSbBiVcxEyqO4Csixpx6UXZb6/E7m y2hiTiunEFGUAXMDcMyC8SHk0S7Ja3qolwW4Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=R1zG/zuBOAUWV8Yn2BOF62J6zPoItYYmv6KFTx1+o64=; b=X0A9Ribh1Ia4+VuDO+2zEuAG75KhdBI/p/GXtVYZxdcZqnGCOWRCl79U+iDy0XHUVJ 65j93TGJRZVh969ZSDnWwFsEAF+qGolQfkAkOYOm9QwYNynFjgjnSi5mBQuKwm7clee/ v7MgOAbhOgEBXj56LZYiDIevu7XcD6jdj5NIK8NgNTQJgUBMReM5ot+2LXe0+DxUFRH3 EbFk6Lov8ofSx073K6rN/df3d0L8T0/7jjdspm3pPQTf/ekfa0Y0hcQQYx0JN0xCmkzf QitDmrdp64dJrjIK4b2NDvDdFYIGxN04N9Ke6guchCZtTgRhP0AiSH65B4muVhwB8nxr z/RA== X-Gm-Message-State: AMCzsaU2/pCdAIYTTw2Q1Vuj2dbG2mG4Enz/6WRjKHJrAguXTfNcYv5u gYTCmEzo1PlXo/zp4oAOmKRWx9smJO4= X-Received: by 10.223.134.25 with SMTP id 25mr3199579wrv.186.1508954394385; Wed, 25 Oct 2017 10:59:54 -0700 (PDT) Received: from localhost.localdomain ([160.161.173.60]) by smtp.gmail.com with ESMTPSA id y29sm3255305wrd.3.2017.10.25.10.59.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Oct 2017 10:59:52 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 25 Oct 2017 18:59:24 +0100 Message-Id: <20171025175947.22798-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms v2 00/23] add support for Socionext Synquacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" This adds support for the Socionext Synquacer SC2A11 evaluation board and revision 0.1 of the Developer Box. It implements support for the core peripherals (CPU, GIC, serial), and for the two PCIe RCs present on this board. (Note that the EVB requires PCI slot CN2 to be populated or it will not boot). Both ACPI and DT hardware descriptions are provided. In ACPI mode, Debian stretch can be booted and installed on PCIe based peripherals, and requires a PCIe based network card that already has upstream support. (On the Developer box, only the x16 slot is supported in this case) The DT description contains references to drivers that are not upstream yet, and will be merged into Linux v4.15 at the earliest. No other OS support is currently planned (as far as I am aware) The non-volatile EFI variable store is backed by the SPI NOR flash, which is therefore not exposed to the OS. Note that it occupies the 'devtree' partition, which must be wiped before use. A driver for the NETSEC network interface is included, which means network boot is supported as well. (Note that this driver deviates in coding style. This code is based on the platform independent driver provided by Socionext, and making cosmetic changes to it will only make it more difficult to track upstream changes) Note that this firmware requires a version of the CM3 firmware that is compatible with the PCIe window configuration as can be found in the file Silicon/Socionext/Synquacer/Include/Platform/Pcie.h (patch #1) Notable gaps in functionality: - no support yet for discovering the amount of DRAM, this in being worked on - no support yet for the I2C RTC on the Developer box Ard Biesheuvel (22): Silicon/SynQuacer: add package with platform headers Silicon/Socionext: add driver for NETSEC network controller Silicon/SynQuacer: add MemoryInitPeiLib implementation Platform: add support for Socionext SynQuacer eval board Silicon/SynQuacer: implement PciSegmentLib to support dual RCs Silicon/SynQuacer: implement PciHostBridgeLib support Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL Platform/SynQuacerEvalBoard: add PCI support Platform/SynQuacerEvalBoard: add NETSEC driver Silicon/SynQuacer: add ACPI support Silicon/SynQuacer: add device tree support for eval board Silicon/SynQuacer: add NorFlashPlatformLib implementation Platform/SynQuacer: incorporate NOR flash and variable drivers Silicon/SynQuacer: implement PlatformFlashAccessLib SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support Socionext/SynQuacerEvalBoard: wire up basic capsule support Socionext/SynQuacerEvalBoard: switch to execute in place Platform/SynQuacerEvalBoard: add signed capsule update support Silicon/SynQuacer/AcpiTables: hide PCI domain #0 Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards Platform/Socionext: add support for Socionext Developer Box rev 0.1 Platform/DeveloperBox: add ConsolePrefDxe driver Pipat Methavanitpong (1): Silicon/Socionext: add driver for SPI NOR flash Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 632 +++++++++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 460 +++++++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 80 ++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 + Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 602 ++++++++ Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 450 ++++++ Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 80 ++ Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 + Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 294 ++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 58 + Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 63 + Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 167 +++ Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 89 ++ Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 98 ++ Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 164 +++ Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 152 ++ Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 + Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 127 ++ Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 21 + Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf | 34 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 515 +++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 21 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf | 34 + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec | 31 + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf | 79 ++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Reg.h | 244 ++++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c | 138 ++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.c | 1376 ++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.h | 314 +++++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c | 859 ++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1005 ++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 47 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 83 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 69 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 263 ++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c | 590 ++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf | 50 + Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 69 + Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 63 + Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 70 + Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf | 41 + Silicon/Socionext/SynQuacer/Library/SynQuacerLib/AArch64/SynQuacerHelper.S | 87 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/Arm/SynQuacerHelper.S | 87 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c | 125 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf | 43 + Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 211 +++ Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 67 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 220 +++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 50 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 392 ++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c | 1398 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf | 35 + Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c | 250 ++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf | 38 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 20 + 75 files changed, 19440 insertions(+) create mode 100644 Platform/Socionext/DeveloperBox/DeveloperBox.dsc create mode 100644 Platform/Socionext/DeveloperBox/DeveloperBox.fdf create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Reg.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf create mode 100644 Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h create mode 100644 Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h create mode 100644 Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c create mode 100644 Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/AArch64/SynQuacerHelper.S create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/Arm/SynQuacerHelper.S create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf create mode 100644 Silicon/Socionext/SynQuacer/SynQuacer.dec -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel