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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id w12-v6si16473149plq.595.2018.05.30.11.19.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GJpVvN0k; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 66762210C997D; Wed, 30 May 2018 11:19:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3892E210C9978 for ; Wed, 30 May 2018 11:19:35 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id v131-v6so30227917wma.1 for ; Wed, 30 May 2018 11:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=EFizt7SKGBTjebLOvQubk7ep+/Ruwb8U+BS6UvNe220=; b=GJpVvN0kL/vrMLpAr+8Xbbx8J8Ka72v9QxmHaqdZ4GS8QSOgjqHFlcEHqgkWG0yEKw hV/GlUbupXMjOLLvN/s02nLiMwltFjkmY84pw8Uqlfn/9s55McCcGchu35ZuSXBeGm8F eZdx3V6/m3G7EO35NeADlUztpzGle5AdR4xbw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=EFizt7SKGBTjebLOvQubk7ep+/Ruwb8U+BS6UvNe220=; b=Tq9W3ReE81h/CVKwASNteGmdGl/DYCyRYTnDro/aguAPb5FBon4a4Cr/98UYbCqeOg a7BhPHQgRc9OoJrPbJ/CtnJEllh1ef7Qio0gMwUXqPLLE9VNZ5GfjdU6Xl09lxPmW7eZ kjNeqUBOEcAjOvMgHNwJOVlrZSS/Zan+RKSf+Ftn3HWZhGEmZu36gOrmaAbTtDGvlB3Y ME9oJDotmz3quB4guaFBS3CA50MJjVijzNMwA78tzsWfGfNlyPqxr7LV4LAWAYTjlTlh 7Fl80lvPEpm934zNrKHAYnSwyLo2112fpi/PplCXbUU8dShVVixc2XR3AUb58ke6BFyu +Nng== X-Gm-Message-State: ALKqPwd3HUuMtBRtvTqrC9JAXHg4LO7+ByV/uDzeKAlT8NyJjqECZA7P 02LZezuyRHoRNY16KfQ2Ivi6gYgLuQI= X-Received: by 2002:a1c:e8c6:: with SMTP id f67-v6mr2076470wmi.25.1527704374067; Wed, 30 May 2018 11:19:34 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:33 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:26 +0200 Message-Id: <20180530181929.5066-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 Subject: [edk2] [PATCH edk2-platforms 0/3] More SynQuacer updates X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Some more patches for SynQuacer, for PCIe and SMMU support. Patch #1 was contributed by Kojima-san, and enables another quirk in the Synopsys IP to work around issues with Samsung 970 SSDs Patch #2 adds a couple of level 3 tables to the static page table region in the NOR flash so that ARM-TF can easily reprogram the north SMMU to present the ECAM spaces in a sane manner. This patch only implements the static page table entries, the code to program it needs to run in the secure world, and will be added to ARM-TF. Patch #3 enables the SMMU for the netsec and SDHCI controllers. Ard Biesheuvel (2): Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT Masahisa KOJIMA (1): Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 .../Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++- .../SynQuacerPciHostBridgeLibConstructor.c | 5 +- .../SynQuacer/Stage2Tables/Stage2Tables.S | 35 ++++-- 3 files changed, 136 insertions(+), 13 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel