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[198.145.21.10]) by mx.google.com with ESMTPS id a5si28446923pfe.203.2016.09.05.02.17.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Sep 2016 02:17:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DB60E1A1E3B; Mon, 5 Sep 2016 02:17:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 956091A1E3B for ; Mon, 5 Sep 2016 02:17:52 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id w2so112582006wmd.0 for ; Mon, 05 Sep 2016 02:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u6JhTR9tXzUOKZ2PP2EGUzWsOJgdhAlLsUmpE2PKcnQ=; b=jNl9JuT52OM7q86Nn/Mge4q9sOWNxgz0Tu0CcbJR1e9CWO779aroCG9II22Y1haot0 L6QpXuFS7Sg7qDoqeoYMvKYvlfVF1DwTL08BFef2ALNMElDU2KZa4kDgya840HBYGtcM pBMKKbE+IWgrTU9kwLjzBHvEQASXrAjxm/FZ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u6JhTR9tXzUOKZ2PP2EGUzWsOJgdhAlLsUmpE2PKcnQ=; b=UuVnlmAGlYdzE7H1xm7t0tzy6MlscNgU+IxKVShUy7RhnWm2KP0VIxSSBnW2ZJUMBl Sskgo/ySBXVz2//XNDkDmrveTepFaezVzw+UvZ+pTjfO9xh4TCny4LTk+QPfFEP/yjPm LQ7RctHx8IhvYlaGoXhCANbyqpXua8ibFgnYtBFMD5e/sd/Eq6UeZTyvOMz4RJaHcpSM ScjL1OZdIvs1i1eLlp6q+jg8XF0zClfGEnm39GVQC9mgNiZAE4beLr83znqPvDmvigMu GqVTrm+ONIPpBGxYQ5lEGlDTLHPbxjPFNGENVk/cNn1Yo0/uQAUey8ZodYZ3gInvLrIS UvfA== X-Gm-Message-State: AE9vXwN28+UtFiqDLbaEEE9a3JVdbmPmDy9f2mB/AsqOhwHQ96leXrSHMoDHMqDLkM49PUCP X-Received: by 10.194.107.163 with SMTP id hd3mr10204863wjb.60.1473067071165; Mon, 05 Sep 2016 02:17:51 -0700 (PDT) Received: from localhost.localdomain ([197.130.133.164]) by smtp.gmail.com with ESMTPSA id m133sm10157457wmg.0.2016.09.05.02.17.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Sep 2016 02:17:50 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, feng.tian@intel.com, star.zeng@intel.com, liming.gao@intel.com Date: Mon, 5 Sep 2016 10:17:26 +0100 Message-Id: <1473067049-16252-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 4/7] MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lersek@redhat.com, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index 0be081dad0bc..5de1dd6fd9e6 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -527,6 +527,7 @@ SdMmcPciHcDriverBindingStart ( CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum; BOOLEAN MediaPresent; + BOOLEAN Support64BitDma; DEBUG ((EFI_D_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); @@ -600,6 +601,7 @@ SdMmcPciHcDriverBindingStart ( goto Done; } + Support64BitDma = TRUE; for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { Private->Slot[Slot].Enable = TRUE; @@ -609,6 +611,8 @@ SdMmcPciHcDriverBindingStart ( } DumpCapabilityReg (Slot, &Private->Capability[Slot]); + Support64BitDma &= Private->Capability[Slot].SysBus64; + Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); if (EFI_ERROR (Status)) { continue; @@ -664,6 +668,22 @@ SdMmcPciHcDriverBindingStart ( } // + // Enable 64-bit DMA support in the PCI layer if this controller + // supports it. + // + if (Support64BitDma) { + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_WARN, "SdMmcPciHcDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status)); + } + } + + // // Start the asynchronous I/O monitor // Status = gBS->CreateEvent (