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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id ww6si27900745pab.52.2016.09.19.01.36.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Sep 2016 01:36:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 11EE51A1E21; Mon, 19 Sep 2016 01:36:25 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22e.google.com (mail-wm0-x22e.google.com [IPv6:2a00:1450:400c:c09::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3A3711A1E08 for ; Mon, 19 Sep 2016 01:36:23 -0700 (PDT) Received: by mail-wm0-x22e.google.com with SMTP id d66so9794928wmf.0 for ; Mon, 19 Sep 2016 01:36:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=huzEYrI60gfBmy8/Th5NrMzbFmjdN3Tq0JE/m5oHUKA=; b=YPDAjaBujaRx7Uv8mqDpvmTb5LsWVcFzYRjzTbpxjxlL6SJ5RvG+pXUuKINksb2Pw3 hglVLkcibAfaOdNkW2XSt9CtG00GKPEMiDSu9AixCxDfVlWiCC606DEmpG3g1Qr5YgcU JLmxZ36UDQr9pCVelI6FMX4CT31HckMn3OOgw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=huzEYrI60gfBmy8/Th5NrMzbFmjdN3Tq0JE/m5oHUKA=; b=ZGCCg3XmQp1lHRjDWFYM/AzM6DK9RFLxt0bKYmdsonyZXkd1c211LMfwfgXHVvAx1c Ct7ar73fnxG6QxlGOhnZSphpnigFtYF1TkcDwQJUOyvvEKdZfQX6wvrNO/kIN8GYrBSo 2sqJhjKRuIuaE3YvA+9dSX8t3INwSFOm0Xxa0xCD6IvSAY20F9WarT4Lri9vj+QmfCAO sX0OUlpp0XnEy2HPhufEaUX0RtOO7mdTPmfTIyzMjUR4aFk5FbeUiz/SrdaFVJIEkDMK /2WwE53fSNr5uVyrq/CKlOTLgCaR/KqWNdbVVBliRygN0m/F/pDfxhSAdghEvQ4XhZe0 B83A== X-Gm-Message-State: AE9vXwNodiNGOeP34T7IzF+tbG5ndkh1/HYtwBPSmZcdTHqZ0P94406yoHBOVxvTBX7JtIq2 X-Received: by 10.28.215.81 with SMTP id o78mr8960870wmg.42.1474274181762; Mon, 19 Sep 2016 01:36:21 -0700 (PDT) Received: from localhost.localdomain ([160.161.71.58]) by smtp.gmail.com with ESMTPSA id jd4sm21845489wjb.6.2016.09.19.01.36.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Sep 2016 01:36:21 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, liming.gao@intel.com, star.zeng@intel.com, feng.tian@intel.com, ruiyu.ni@intel.com, leif.lindholm@linaro.org, afish@apple.com, michael.d.kinney@intel.com Date: Mon, 19 Sep 2016 09:36:13 +0100 Message-Id: <1474274173-8432-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [edk2] [PATCH v2] MdeModulePkg/PciBusDxe: make OPROM BAR degradation configurable X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiewen.yao@intel.com, lersek@redhat.com, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The 'universal' PCI bus driver in MdeModulePkg contains a quirk to degrade 64-bit PCI MMIO BARs to 32-bit in the presence of an option ROM on the same PCI controller. This quirk is highly specific to not just the X64 architecture in general, but to the PC platform in particular, given that only X64 platforms that require legacy PC BIOS compatibility require it. However, making the quirk dependent on the presence of the legacy BIOS protocol met with resistance, due to the fact that it introduces a dependency on the IntelFrameworkModulePkg package. So instead, make the quirk configurable, by introducing a feature flag PCD which defaults to TRUE only for X64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- v2: followed the suggestion of Andrew Fish to introduce a new feature flag PCD that controls the PCI BAR degradation behavior. MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 76 ++++++++++---------- MdeModulePkg/MdeModulePkg.dec | 12 ++++ 3 files changed, 52 insertions(+), 37 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf index 330ccc8cbffc..fc49f3d9412c 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -100,6 +100,7 @@ [FeaturePcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdUnalignedPciIoEnable ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeBarsForOptionRom ## CONSUMES [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize ## SOMETIMES_CONSUMES diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index b0632d53b82b..37dc03e90358 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -1058,48 +1058,50 @@ DegradeResource ( LIST_ENTRY *NextChildNodeLink; PCI_RESOURCE_NODE *ResourceNode; - // - // If any child device has both option ROM and 64-bit BAR, degrade its PMEM64/MEM64 - // requests in case that if a legacy option ROM image can not access 64-bit resources. - // - ChildDeviceLink = Bridge->ChildList.ForwardLink; - while (ChildDeviceLink != NULL && ChildDeviceLink != &Bridge->ChildList) { - PciIoDevice = PCI_IO_DEVICE_FROM_LINK (ChildDeviceLink); - if (PciIoDevice->RomSize != 0) { - if (!IsListEmpty (&Mem64Node->ChildList)) { - ChildNodeLink = Mem64Node->ChildList.ForwardLink; - while (ChildNodeLink != &Mem64Node->ChildList) { - ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); - NextChildNodeLink = ChildNodeLink->ForwardLink; - - if ((ResourceNode->PciDev == PciIoDevice) && - (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) - ) { - RemoveEntryList (ChildNodeLink); - InsertResourceNode (Mem32Node, ResourceNode); + if (FeaturePcdGet (PcdPciDegradeBarsForOptionRom)) { + // + // If any child device has both option ROM and 64-bit BAR, degrade its PMEM64/MEM64 + // requests in case that if a legacy option ROM image can not access 64-bit resources. + // + ChildDeviceLink = Bridge->ChildList.ForwardLink; + while (ChildDeviceLink != NULL && ChildDeviceLink != &Bridge->ChildList) { + PciIoDevice = PCI_IO_DEVICE_FROM_LINK (ChildDeviceLink); + if (PciIoDevice->RomSize != 0) { + if (!IsListEmpty (&Mem64Node->ChildList)) { + ChildNodeLink = Mem64Node->ChildList.ForwardLink; + while (ChildNodeLink != &Mem64Node->ChildList) { + ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); + NextChildNodeLink = ChildNodeLink->ForwardLink; + + if ((ResourceNode->PciDev == PciIoDevice) && + (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) + ) { + RemoveEntryList (ChildNodeLink); + InsertResourceNode (Mem32Node, ResourceNode); + } + ChildNodeLink = NextChildNodeLink; } - ChildNodeLink = NextChildNodeLink; - } - } + } - if (!IsListEmpty (&PMem64Node->ChildList)) { - ChildNodeLink = PMem64Node->ChildList.ForwardLink; - while (ChildNodeLink != &PMem64Node->ChildList) { - ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); - NextChildNodeLink = ChildNodeLink->ForwardLink; - - if ((ResourceNode->PciDev == PciIoDevice) && - (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) - ) { - RemoveEntryList (ChildNodeLink); - InsertResourceNode (PMem32Node, ResourceNode); + if (!IsListEmpty (&PMem64Node->ChildList)) { + ChildNodeLink = PMem64Node->ChildList.ForwardLink; + while (ChildNodeLink != &PMem64Node->ChildList) { + ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); + NextChildNodeLink = ChildNodeLink->ForwardLink; + + if ((ResourceNode->PciDev == PciIoDevice) && + (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) + ) { + RemoveEntryList (ChildNodeLink); + InsertResourceNode (PMem32Node, ResourceNode); + } + ChildNodeLink = NextChildNodeLink; } - ChildNodeLink = NextChildNodeLink; - } - } + } + } + ChildDeviceLink = ChildDeviceLink->ForwardLink; } - ChildDeviceLink = ChildDeviceLink->ForwardLink; } // diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 8d90f169b26e..d8cb9c119598 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -749,6 +749,18 @@ [PcdsFeatureFlag] # @Prompt Turn on PS2 Mouse Extended Verification gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|TRUE|BOOLEAN|0x00010075 +[PcdsFeatureFlag.X64] + ## Indicates whether 64-bit PCI MMIO BARs should degrade to 32-bit in the presence of an option ROM + # On X64 platforms, Option ROMs may contain code that executes in the context of a legacy BIOS (CSM), + # which requires that all PCI MMIO BARs are located below 4 GB + # TRUE - All PCI MMIO BARs of a device will be located below 4 GB if it has an option ROM + # FALSE - PCI MMIO BARs of a device may be located above 4 GB even if it has an option ROM + # @Prompt Degrade 64-bit PCI MMIO BARs for legacy BIOS option ROMs + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeBarsForOptionRom|TRUE|BOOLEAN|0x0001003a + +[PcdsFeatureFlag.IA32, PcdsFeatureFlag.ARM, PcdsFeatureFlag.AARCH64] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeBarsForOptionRom|FALSE|BOOLEAN|0x0001003a + [PcdsFeatureFlag.IA32, PcdsFeatureFlag.X64] ## Indicates if DxeIpl should switch to long mode to enter DXE phase. # It is assumed that 64-bit DxeCore is built in firmware if it is true; otherwise 32-bit DxeCore